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®
Data Sheet
Wide Input Range Dual PWM Controller
with DDR Option
The ISL6539 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. It was designed especially for DDR DRAM,
SDRAM, graphic chipset applications, and system regulators in
high performance applications.
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel-to-channel PWM
phase shift of 0°, 90°, or 180° (determined by input voltage
and status of the DDR pin).
The ISL6539 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
In dual power supply applications the ISL6539 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within PGOOD window. In DDR mode CH1
generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage decays
below the overvoltage threshold, normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value
for the dual switcher. Adjustable overcurrent protection (OCP)
monitors the voltage drop across the rDS(ON) of the lower
MOSFET. If more precise current-sensing is required, an
external current sense resistor may be used.
ISL6539
May 2004
FN9144.3
Features
• Provides regulated output voltage in the range 0.9V–5.5V
• Complete DDR memory power solution with VTT tracks
VDDQ/2 and VDDQ/2 buffered reference output
• Supports both DDR-I and DDR2 memory
• Lossless rDS(ON) current-sense sensing
• Excellent dynamic response with voltage feed-forward and
current mode control accommodating wide range LC filter
selections
• Dual mode operation–operates directly from a 5.0-15V
input or 3.3V/5V system rail
• Undervoltage lock-out on VCC pin
• Power-good, overcurrent, overvoltage, undervoltage
protection for both channels
• Synchronized 300kHz PWM operation in PWM mode
• Pb-Free Available
Applications
Single and Dual Channel DDR Memory Power Systems
Graphics cards - GPU and memory supplies
• Supplies for Servers, Motherboards, FPGAs
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6539
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6539CA
0 to 70 28 Ld SSOP
M28.15
ISL6539CA-T
28 Ld SSOP Tape and Reel
ISL6539CAZ (Note) 0 to 70 28 Ld SSOP (Pb-Free) M28.15
ISL6539CAZ-T
(Note)
28 Ld SSOP Tape and Reel (Pb-Free)
ISL6539IA
-40 to 85 28 Ld SSOP
M28.15
ISL6539IA-T
28 Ld SSOP Tape and Reel
ISL6539IAZ (Note) -40 to 85 28 Ld SSOP (Pb-Free) M28.15
ISL6539IAZ-T
(Note)
28 Ld SSOP Tape and Reel (Pb-Free)
NOTE: Intersil Pb-Free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-Free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6539 (SSOP)
TOP VIEW
GND 1
LGATE1 2
PGND1 3
PHASE1 4
UGATE1 5
BOOT1 6
ISEN1 7
EN1 8
GND 9
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 GND
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
2

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Generic Application Circuits
VIN
3.3V OR
5.0V TO 15V
OCSET1
EN1
EN2
VCC
5V
DDR
OCSET2
ISL6539
PWM1
PWM2
Q1 L1
+
Q2 C1
VOUT1
Q3
L2
VOUT2
+
Q4 C2
ISL6539 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY
VIN
3.3V OR
5.0V TO 15V
VREF
5V
OCSET1
EN1
EN2
VCC
DDR
PG2/VREF
PWM1
PWM2
Q1
L1
+
Q2 C1
VDDQ
OCSET2
Q3
L2
VTT
+
Q4 C2
ISL6539 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY
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ISL6539
ABOOTbsolute Maximum Ratings
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18.0V
PHASE, UGATE . . . . . . . . . . . . . . . . . . .GND-5V (Note 1) to +24.0V
BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to +24.0V
BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature (Plastic Package). . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SSOP - Lead Tips Only)
Recommended Operating Conditions
Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V ±5%
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . +3.3V or 5.0V to +18.0V
Ambient Temperature Range, Commercial . . . . . . . . . . 0°C to 70°C
Junction Temperature Range, Commercial . . . . . . . . . 0°C to 125°C
Ambient Temperature Range, Industrial. . . . . . . . . . . .-40°C to 85°C
Junction Temperature Range, Industrial . . . . . . . . . .-40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. 250ns transient. See Confining The Negative Phase Node Voltage Swing in Application Information Section.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER
SYMBOL
TEST CONDITIONS
VCC SUPPLY
Bias Current
ICC LGATEx, UGATEx Open, VSENx forced above
regulation point, DDR = 0, VIN > 5V
Shut-down Current
VCC UVLO
ICCSN
Rising VCC Threshold
Falling VCC Threshold
VIN
VCCU
VCCD
Input Voltage Pin Current (Sink)
Shut-down Current
OSCILLATOR
IVIN
IVINS
Oscillator Frequency
Ramp Amplitude, pk-pk
Ramp Amplitude, pk-pk
Ramp Offset
Ramp/VIN Gain
Ramp/VIN Gain
REFERENCE AND SOFT-START
fOSC
VR1
VR2
VROFF
GRB1
GRB2
Vin pin voltage = 16V, by design
Vin pin voltage = 5V, by design
By design
Vin pin voltage > 4.2V, by design
Vin pin voltage 4.1V by design
Internal Reference Voltage
Reference Voltage Accuracy
VREF
Soft-Start Current During Start-up
Soft-Start Complete Threshold
ISOFT
VST
By design
MIN TYP MAX UNITS
- 1.8 3.0 mA
- - 1 µA
4.30
4.00
4.45
4.14
4.50
4.34
V
V
- - 35 µA
- - 1 µA
255 300 345 kHz
-2-V
- 0.625 -
V
-1-V
- 125 - mV/V
- 250 - mV/V
- 0.9 -
V
-1.0
-
+1.0
%
- 4.5 - µA
- 1.5 -
V
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ISL6539
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PWM CONVERTERS
Load Regulation
VSEN pin bias current
Minimum Duty Cycle
Maximum Duty Cycle
Undervoltage Shut-Down Level
Overvoltage Protection
GATE DRIVERS
IVSEN
DMIN
DMAX
VUVL
VOVP1
0.0mA < IVOUT1 < 5.0A; 5.0V < VIN < 15.0V
By design
Fraction of the set point; ~2ms noise filter
Fraction of the set point; ~2ms noise filter
-2.0
-
-
-
70
110
Upper Drive Pull-Up Resistance
R2UGPUP
Upper Drive Pull-Down Resistance
R2UGPDN
Lower Drive Pull-Up Resistance
R2LGPUP
Lower Drive Pull-Down Resistance
R2LGPDN
POWER GOOD AND CONTROL FUNCTIONS
VCC = 5V
VCC = 5V
VCC = 5V
VCC = 5V
-
-
-
-
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
ISEN sourcing current
VPG-
VPG+
IPGLKG
VPGOOD
Fraction of the set point; ~3ms noise filter
Fraction of the set point; ~3ms noise filter.
VPULLUP = 5.5V
IPGOOD = -4mA
By design
84
110
-
-
-
OCSET sourcing current range
2
EN - Low (Off)
-
EN - High (On)
2.0
DDR - Low (Off)
-
DDR - High (On)
3
DDR REF Output Voltage
DDR REF Output Current
VDDREF DDR = 1, IREF = 0...10mA
IDDREF DDR = 1. Guaranteed by design.
0.99*
VOC2
-
TYP
-
80
4
87
75
115
4
2.3
4
1.1
89
115
-
0.5
-
-
-
-
-
-
VOC2
10
MAX UNITS
+2.0
-
-
-
80
-
%
nA
%
%
%
%
8
4
8
3
92
120
1
1
260
20
0.8
-
0.8
-
1.01*
VOC2
12
%
%
µA
V
µA
µA
V
V
V
V
V
mA
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
5