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®
Data Sheet
ISL6550A, ISL6550B, ISL6550C
July 2003
FN9036.2
SAM (Supervisor And Monitor)
The ISL6550 is a precision, flexible, VID-code-controlled
reference and voltage monitor for high-end microprocessor
and memory power supplies. It monitors various input
signals, and supervises the system (typically a DC/DC
converter) with its output signals. See the Block Diagram for
reference.
The ISL6550 includes a 5-bit DAC (Digital-to-Analog
Converter), which is programmed by the five VID inputs. The
voltage range of the BDAC (Buffered DAC output) is
determined by the DACHI and DACLO voltage levels, which
are externally adjustable through the R1, R2, R3 resistor
divider network. VREF5 is a precision-trimmed 5V reference,
and is used to set the voltage at the top of the resistor
divider.
Programmable window comparators monitor Over-Voltage
(OV) and Under-Voltage (UV) levels. The OVUVSEN input,
usually coming from the associated power converter device
is monitored and compared with BDAC; an error band is
established via the R4 and R5 resistor setting on the
OVUVTH pin. An optional external capacitor on the UVDLY
pin gives a programmable delay on the UV. A high gain
operational amplifier is available at pins VOPP, VOPM, and
VOPOUT; it can be used as a gain stage to permit
monitoring voltages that are different from the BDAC levels.
The PEN (Power supply ENable) input, driven from an open-
collector source, enables (when logic high) the external
converter output, via the PGOOD or START outputs (both
open-drain). They both basically indicate that the power
supply is enabled (PEN = high) and there are no fault
conditions. There are three logic options available, which
determine the START and PGOOD states; see the block
diagram or the Logic Options Table for more detail. The
three logic options are identified with a suffix letter A, B, or C
in the ordering information.
Features
• 12V supply operation
• 5V reference output
• 5-bit digital-to-analog converter
• Programmable DAC Range, within 0.8–5.0V
• Programmable undervoltage and overvoltage thresholds,
and latched fault detection
• Optional delayed undervoltage (programmable with
external capacitor)
• Undervoltage lockout (power-on-reset)
• Status Indicators (START, PGOOD)
• Uncommitted operational amplifier
• Compatible with ISL6551 full bridge controller
• 20 Lead SOIC and 20 lead QFN (5x5) packages
Applications
• Power Supplies for High End Microprocessors and Servers
• Can be paired with the ISL6551 FBC for a complete full-
bridge 48V-input converter, or used independently
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC) PACKAGE PKG. DWG. #
ISL6550AIB
-40 to 85 20 Lead SOIC M20.3
ISL6550BIB
-40 to 85 20 Lead SOIC M20.3
ISL6550CIB
-40 to 85 20 Lead SOIC M20.3
ISL6550AIR
-40 to 85 20 Lead QFN L20.5x5
ISL6550BIR
-40 to 85 20 Lead QFN L20.5x5
ISL6550CIR
-40 to 85 20 Lead QFN L20.5x5
NOTE: The same part numbers with a “-T” suffix are available as
Tape and Reel.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

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ISL6550A, ISL6550B, ISL6550C
Pinout
20 PIN WIDE BODY (SOIC)
TOP VIEW
VCC 1
VOPP 2
VOPM 3
VOPOUT 4
VREF5 5
GND 6
BDAC 7
OVUVTH 8
DACHI 9
DACLO 10
20 UVDLY
19 OVUVSEN
18 PGOOD
17 START
16 PEN
15 VID0
14 VID1
13 VID2
12 VID3
11 VID4
20 PIN 5X5 (QFN)
TOP VIEW
20 19 18 17 16
VID1 1
VID0 2
15 OVUVTH
14 BDAC
PEN 3
13 GND
START 4
PGOOD 5
12 VREF5
11 VOPOUT
6 7 8 9 10
2

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ISL6550A, ISL6550B, ISL6550C
Block Diagram
VOPM 3
VOPP 2
VOPOUT 4
PEN 16
OPAMP
-
+
10µA TO 5V
VREF5
5
5V
VCC
1
BUFFERED
5V REF
LOGIC BLOCK
SEE OPTIONS A, B, C BELOW
PEN: H = ENABLE; L = DISABLE
ST
OVUVSEN 19
OVUVTH 8
THRESHOLD
PROGRAM
R1
UVLOCKOUT
(POR)
OV
UV
UV/OV HYST:
SEE NOTE
BELOW
POR: H = VDD TOO LOW; L = VDD OK
OV: H = OVER-VOLTAGE; L = OK
UV: H = UNDER-VOLTAGE; L = OK
UVD: H = UV DELAY TIMED OUT;
L = NO TIME-OUT
PG
DACHI 9
(EACH VID PIN)
VID4 11
10µA TO 5V
VID3 12
VID2 13
VID1 14
R2 VID0 15
5-BIT
DAC
UVDELAY
DAC _BUFFER
DACLO 10
R3
6
GND
NOTE: Pin numbers shown are for the 20 lead SOIC package. Please check PINOUT diagrams for QFN pin numbers.
A
NOTE: UV/OV
Hysteresis = 10%
PEN
POR
Q
B
NOTE: UV/OV
ST Hysteresis = 40%
PEN
POR
OV
UVD
C
NOTE: UV/OV
ST
Hysteresis = 10%
PEN
POR
Q
RST
17 START
RPG
18 PGOOD
20 UVDLY
(OPT)
C1
7 BDAC
R4
R5
ST
POR
UV
UVD
PEN
OV
R
Q Q: H = FAULT;
L = NO FAULT
S
FAULT
LATCH
NOTE: S input dominates Q
PEN
POR
Q
UV
PG
NOTE: No latch in B
PEN
POR
OV
UV
POR
PEN
UV
UVD
PEN
OV
R
Q Q: H = FAULT;
L = NO FAULT
S
FAULT
LATCH
POR
PG OV
UV
NOTE: S input dominates Q
PG
3

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ISL6550A, ISL6550B, ISL6550C
Pin Descriptions
NOTE: Pin numbers refer to the 20 lead SOIC package. Please
check PINOUT diagrams for QFN pin numbers.
VCC (Positive Supply Voltage) Pin 1 - This power pin
supplies power to the IC; nominally 12V. It should be
bypassed directly to the GND pin with a 0.1µF low ESR/ESL
capacitor.
GND (Signal Ground) Pin 6 - This power pin is the
reference ground connection for the IC, and any circuitry that
provides input/output to/from it.
VID0-VID4 (DAC Digital Input Code Control) Pins 15-11 -
These are the DAC digital input control code lines. VID0
represents the least significant bit (LSB) and VID4
represents the most significant bit (MSB). Table 1 shows all
of the codes, and their results. Note that setting all input
codes low produces the maximum voltage at BDAC. The
minimum voltage results when all codes are set high. Logic
zero is considered system ground. A floated input or an input
held higher than 2.0V is considered a logic one level. An
internal 10µA current source pulls open VID pins to a logic
high (nominal 1.6V). The pins are also TTL and LVTTL
compatible.
PEN (Power Supply Enable) Pin 18 - This digital input pin
enables the external converter through the START or
PGOOD pins. A logic high (or float) enables the output
voltage, and a logic low disables it. This pin has a 10µA pull-
up current source, so it can interface with an open-collector
or open-drain driver. When disabled, the START output is
low and the PGOOD output is low.
OVUVTH (Over-Voltage/Under-Voltage THreshold) Pin 8 -
This analog input pin is used to program the window
thresholds for the OV and UV comparators. The OV-UV
window is centered around the BDAC voltage and can be
programmed from ±5% to ±40% about the BDAC voltage.
This pin’s voltage sets the undervoltage threshold. Internal
circuitry sets the overvoltage threshold such that the two
thresholds are centered about BDAC, the DAC output
voltage. For example, if BDAC is 2.5V, and OVUVTH is 2.0V
(0.5V below BDAC), then the internal OV threshold is 3.0V
(0.5V above BDAC).
OVUVSEN (Over-Voltage/Under-Voltage SENse) Pin 19 -
This analog input pin is the sense voltage for Under-Voltage
and Over-Voltage purposes. A resistor divider from the
BDAC output sets the UV level, on the OVTH/UVTH pin; the
IC will internally mirror a similar voltage for OV, and then
compare them both to the OVUVSEN input.
DACHI (HIgh Limit of BDAC Voltage Range) Pin 9 - This
analog input pin sets the high level of the BDAC, and is
programmed through the external 3-resistor divider (R1, R2,
R3) shown in the block diagram.
DACLO (LOw Limit of BDAC Voltage Range) Pin 10 -
This analog input pin sets the low level of the BDAC, and is
programmed through the external 3-resistor divider shown in
the block diagram.
NOTE: A total resistance of around 50K is optimal for R1, R2, and
R3. Adjust the ratios of these resistors to get the desired DACHI and
DACLO voltage levels.
UVDLY (Under Voltage Delay) Pin 20 - This is an analog
input/output pin. When the Under-Voltage threshold is
exceeded, a potential fault is detected. A capacitor tied to
the UVDLY pin is charged by an internal 10 uA source. The
ramp time of the capacitor to the threshold voltage (5V
nominal) determines the delay. (no capacitor gives
essentially no delay).
VOPP (Positive Opamp Input) Pin 2 - This analog input pin
is the positive input of the Opamp.
VOPM (Minus Opamp Input) Pin 3 - This analog input pin
is the minus input of the Opamp.
VOPOUT (Opamp Output) Pin 4 - This analog output pin is
the output of the Opamp.
BDAC (Buffered Digital-to-Analog Converter) Pin 7 -
This analog output pin is the output of the 5-bit DAC. Setting
all input codes low produces the maximum voltage at BDAC.
The minimum voltage results when all codes are set high.
See Table 1 for codes.
VREF5 (5 Volt Reference Voltage) Pin 5 - This is an
analog output pin, which provides a precision reference
voltage for setting DACHI and DACLO voltage levels.
START Pin 17 - This is an open-drain pull-down digital
output pin; it is pulled low when one or more of the monitored
conditions is not valid; the output goes high impedance (to
be pulled high externally through a pull-up resistor or
equivalent) if all conditions are met. See Logic Options Table
for the various conditions.
PGOOD (Power Good) Pin 18 - This is an open-drain pull-
down digital output pin; it is pulled low when one or more of
the monitored conditions is not valid; the output goes high
impedance (to be pulled high externally through a pull-up
resistor or equivalent)) if all conditions are met. See Logic
Options Table for the various conditions.
4

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ISL6550A, ISL6550B, ISL6550C
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance
θJA (oC/W) θJC (oC/W)
SOIC Package (Typical, Note 1) . . . . .
65
N/A
QFN Package (Typical, Note 2) . . . . . .
35
5
Maximum Junction Temperature (Plastic Package) . .
150
Maximum Storage Temperature Range . . . . . . . . . . . -65 to 150
Maximum Lead Temperature (Soldering 10s) . . . . . . .
300
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications TA = 25oC, and VDD = 12V, unless otherwise specified
PARAMETER
SYMBOL
TEST CONDITIONS
SUPPLY CURRENT
Input Current
UNDER-VOLTAGE LOCKOUT
IIN VCC = 12V
VCC UVLO Turn-on Threshold
VCC UVLO Turn-off Threshold
VCC UVLO Threshold Hysteresis
DAC REFERENCE
DAC Output Error (See Notes 3, 4)
Step Size = 25mV
Vdaclo = 0.8V to 4.225V
Ibdac = 0.1mA to -1mA
DAC Output Error (See Notes 3, 4)
Step Size = 50mV
Vdaclo = 0.8V to 3.45V
Ibdac = 0.1mA to -1mA
DAC Output Error (See Notes 3, 4)
Step Size = 100mV
Vdaclo = 0.8V to 1.9V
Ibdac = 0.1mA to -1mA
VREF5 Voltage
VID0-VID4 Input LPUL (Vih)
VID0-VID4 Input MPDL (Vil)
VID0-VID4 Input Pull-Up Current
Vvidx = 0V
VID0-VID4 Input Leakage Current
Vvidx = 5V
Output Settling Time
±1LSB Error Band
UVDLY
Source Current
Sink Current
Threshold
MIN
TYP
MAX
UNITS
- 5 6 mA
9.2 9.4 9.9
8.2 8.4 8.9
- 1.0 -
-
-
-
-2 - +2 mV
-2 - +4 mV
-2 - +6 mV
4.95 - 5.05 V
2.0 - - V
- - 0.8 V
-15 -10 - mA
- - 1 µA
- - 20 µS
- -10 -
µA
- 10 - mA
-5- V
5