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DATASHEET
ZVS Full Bridge PWM Controller
ISL6551
The ISL6551 is a zero voltage switching (ZVS) full-bridge PWM
controller designed for isolated power systems. This part
implements a unique control algorithm for fixed-frequency ZVS
current mode control, yielding high efficiency with low EMI. The
two lower drivers are PWM controlled on the trailing edge and
employ resonant delay while the two upper drivers are driven
at a fixed 50% duty cycle.
This IC integrates many features in 28 Ld SOIC package to
yield a complete and sophisticated power supply solution.
Control features include programmable soft-start for
controlled start-up, programmable resonant delay for zero
voltage switching, programmable leading edge blanking to
prevent false triggering of the PWM comparator due to the
leading edge spike of the current ramp, adjustable ramp for
slope compensation, drive signals for implementing
synchronous rectification in high output current, ultra high
efficiency applications and current share support for
paralleling up to 10 units, which helps achieve higher reliability
and availability as well as better thermal management.
Protective features include adjustable cycle-by-cycle peak
current limiting for overcurrent protection, fast short-circuit
protection (in hiccup mode), a latching shutdown input to turn
off the IC completely on output overvoltage conditions or other
extreme and undesirable faults, a non-latching enable input to
accept an enable command when monitoring the input voltage
and thermal condition of a converter and VDD undervoltage
lockout with hysteresis. Additionally, the ISL6551 includes
high current high-side and low-side totem-pole drivers to avoid
additional external drivers for moderate gate capacitance (up
to 1.6nF at 1MHz) applications, an uncommitted high
bandwidth (10MHz) error amplifier for feedback loop
compensation, a precision bandgap reference with ±1.5%
(ISL6551AB) or ±1% (ISL6551IB) tolerance across
recommended operating conditions and a ±5% “in regulation”
monitor.
In addition to the ISL6551, other external elements such as
transformers, pulse transformers, capacitors, inductors and
Schottky or synchronous rectifiers are required for a complete
power supply solution. A detailed 200W telecom power supply
reference design using the ISL6551 with companion Intersil
ICs, Supervisor and Monitor ISL6550, and Half-bridge Driver
HIP2100, is presented in application note AN1002.
In addition, the ISL6551 can also be designed in push-pull
converters using all of the features except the two upper
drivers and adjustable resonant delay features.
Features
• High speed PWM (up to 1MHz) for ZVS full bridge control
• Current mode control compatible
• High current high-side and low-side totem-pole drivers
• Adjustable resonant delay for ZVS
• 10MHz error amplifier bandwidth
• Programmable soft-start
• Precision bandgap reference
• Latching shutdown input
• Non-latching enable input
• Adjustable leading edge blanking
• Adjustable dead time control
• Adjustable ramp for slope compensation
• Fast short-circuit protection (hiccup mode)
• Adjustable cycle-by-cycle peak current limiting
• Drive signals to implement synchronous rectification
• VDD undervoltage lockout
• Current share support
• ±5% “in regulation” indication
• Pb-free (RoHS compliant)
Applications
• Full-bridge and push-pull converters
• Power supplies for off-line and Telecom/Datacom
• Power supplies for high end microprocessors and servers
Related Literature
AN1002, 200W, 470kHz, Telecom Power Supply Using
ISL6551 Full-Bridge Controller and ISL6550 Supervisor and
Monitor.
April 30, 2015
FN9066.6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2003-2006, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
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ISL6551
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Drive Signals Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagram Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Shutdown Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Shutdown Timing Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block/Pin Functional Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Additional Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Blocks Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Primary FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Main Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supervisor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Primary FET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Full Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Simplified Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Small Outline Plastic Packages (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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ISL6551
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6551IBZ
ISL6551IBZ
0 to +85
28 Ld SOIC
M28.3
ISL6551ABZ
ISL6551ABZ
-40 to +105
28 Ld SOIC
M28.3
NOTES:
1. Add “-T” suffix for tape and reel.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL6551. For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL6551
28 LD (SOIC)
TOP VIEW
VSS 1
CT 2
RD 3
R_RESDLY 4
R_RA 5
ISENSE 6
PKILIM 7
BGREF 8
R_LEB 9
CS_COMP 10
CSS 11
EANI 12
EAI 13
EAO 14
28 VDD
27 VDDP1
26 VDDP2
25 PGND
24 UPPER1
23 UPPER2
22 LOWER1
21 LOWER2
20 SYNC1
19 SYNC2
18 ON/OFF
17 DCOK
16 LATSD
15 SHARE
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ISL6551
Functional Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19, 20
21, 22
23, 24
25
26, 27
28
PIN NAME
VSS
CT
RD
R_RESDLY
R_RA
ISENSE
PKILIM
BGREF
R_LEB
CS_COMP
CSS
EANI
EAI
EAO
SHARE
LATSD
DCOK
ON/OFF
SYNC2, SYNC1
LOWER2, LOWER1
UPPER2, UPPER1
PGND
VDDP2, VDDP1
VDD
DESCRIPTION
Reference ground. All control circuits are referenced to this pin.
Set the oscillator frequency, up to 1MHz.
Adjust the clock dead time from 50ns to 1000ns.
Program the resonant delay from 50ns to 500ns.
Adjust the ramp for slope compensation (from 50mV to 250mV).
The pin receives the current information via a current sense transformer or a power resistor.
Set the overcurrent limit with the bandgap reference as the trip threshold.
Precision bandgap reference, 1.263V ±2% overall recommended operating conditions.
Program the leading edge blanking from 50ns to 300ns.
Set a low current sharing loop bandwidth with a capacitor.
Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.
Noninverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).
Inverting input of error amp. It receives the feedback voltage.
Output of error amp. It is clamped by the voltage at the CSS pin (Vclamp).
This pin is the SHARE BUS connecting with other unit(s) for current share operation.
The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.
Power-good indication with a ±5% window.
This is an Enable pin that controls the states of all drive signals and the soft-start.
These are the gate control signals for the output synchronous rectifiers.
Both lower drivers are PWM controlled on the trailing edge.
Both upper drivers are driven at a fixed 50% duty cycle.
Power ground. High current return paths for both the upper and the lower drivers.
Power is delivered to both the upper and the lower drivers through these pins.
Power is delivered to all control circuits including SYNC1 and SYNC2 via this pin.
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Functional Block Diagram
ISL6551
BANDGAP
REFERENCE
BGREF 8
PKILIM 7
R_LEB 9
R_RESDLY 4
RESODLY
ISENSE 6
R_RA 5
CT 2
RD 3
EAO 14
RAMP
ADJUST
CLOCK
GENERATOR
ERROR AMP
Figure 7
EAI 13
EANI 12
DC OK
UVLO
SSHHUUTTDDOOWWNN
LLAATTCCHH
SSOOFFT-T
SSTTAARRTT
SSHHUUTTDDOOWWNN
UPPER1
DRIVER
27 VDDP1
24 UPPER1
LEB
PWM
LOGIC
UPPER2
DRIVER
23 UPPER2
LOWER1
DRIVER
26 VDDP2
22 LOWER1
CURRENT
SHARE
LOWER2
DRIVER
21 LOWER2
CIRCUITS REFERENCED TO VSS
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CIRCUITS REFERENCED TO PGND
EXTERNAL SINGLE POINT CONNECTION REQUIRED
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN9066.6
April 30, 2015