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August 2004
ISL6553
FN4931.1
Microprocessor CORE Voltage Regulator
Multi-Phase Buck PWM Controller
The ISL6553 multi-phase PWM control IC together with its
companion gate drivers, the HIP6601, HIP6602 or HIP6603
provides a precision voltage regulation system for advanced
microprocessors. Multi-phase power conversion is a marked
departure from earlier single phase converter configurations
previously employed to satisfy the ever increasing current
demands of modern microprocessors. Multi-phase
converters, by distributing the power and load current results
in smaller and lower cost transistors with fewer input and
output capacitors. These reductions accrue from the higher
effective conversion frequency with higher frequency ripple
current due to the phase interleaving process of this
topology. For example, a two phase converter operating at
350kHz will have a ripple frequency of 700kHz. Moreover,
greater converter bandwidth of this design results in faster
response to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.05V to 1.825V with a system accuracy of 1%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors. In addition “droop” compensation,
used to reduce the overshoot or undershoot of the CORE
voltage, is easily programmed with a single resistor.
Another feature of this controller IC is the PGOOD monitor
circuit which is held low until the CORE voltage increases,
during its Soft-Start sequence, to within 10% of the
programmed voltage. Over-voltage, 15% above
programmed CORE voltage, results in the converter shutting
down and turning the lower MOSFETs ON to clamp and
protect the microprocessor. Under voltage is also detected
and results in PGOOD low if the CORE voltage falls 10%
below the programmed level. Over-current protection
reduces the regulator RMS output current to 41% of the
programmed over-current trip value. These features provide
monitoring and protection for the microprocessor and power
system.
Features
• Multi-Phase Power Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses rDS(ON)
• Precision CORE Voltage Regulation
- 1% System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.05V to 1.825V in 25mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency, (Channel Frequency) Times
Number Channels . . . . . . . . . . . . . . . . . .100kHz to 3MHz
• Pb-free available
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE
ISL6553CB
0 to 70 16 Ld SOIC
ISL6553CBZ (Note)
0 to 70
16 Ld SOIC
(Pb-free)
ISL6553EVAL1
Evaluation Platform
*Add “-T” suffix to part number for tape and reel packaging.
PKG. DWG.
#
M16.15
M16.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6553 (SOIC)
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
VID25mV 5
COMP 6
FB 7
FS/DIS 8
16 VCC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Block Diagram
ISL6553
PGOOD
VCC
VSEN
X 0.9
X1.15
+
UV
-
+
OVP
-
OV
LATCH
S
POWER-ON
RESET (POR)
CLOCK AND
SAWTOOTH
GENERATOR
THREE
STATE
FS/EN
COMP
SOFT-
START
AND FAULT
LOGIC
+
-
VID3
VID2
VID1
VID0
VID25mV
FB
+
-
D/A
+
E/A
-
I_TOT
CURRENT
CORRECTION
+
OC
-
+
+
I_TRIP
GND
Simplified Power System Diagram
VSEN
ISL6553
PWM 1
PWM 2
VID
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
+
PWM
-
+
PWM
-
PWM1
PWM2
ISEN1
ISEN2
MICROPROCESSOR
2

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ISL6553
Functional Pin Description
VID3 1
VID2 2
VID1 3
VID0 4
VID25mV 5
COMP 6
FB 7
FS/DIS 8
16 VCC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)
and VID25mV (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The ISL6553 decodes
VID bits to establish the output voltage. See Table 1.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
FB (Pin 7)
Inverting input of the internal error amplifier.
FS/DIS (Pin 8)
Channel frequency, FSW, select and disable. A resistor from
this pin to ground sets the switching frequency of the
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessor-
CORE voltage.
ISEN2 (Pin 11) and ISEN1 (Pin 14)
Current sense inputs from the individual converter channel’s
phase nodes.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver.
PGOOD (Pin 15)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
VCC (Pin 16)
Bias supply. Connect this pin to a 5V supply.
Typical Application - Two Phase Converter Using HIP6601 Gate Drivers
+12V
PVCC
BOOT
UGATE
VCC
PHASE
DRIVER
+5V PWM HIP6601 LGATE
GND
VIN = +5V
+VCORE
PGOOD
VID3
VID2
VID1
VID0
VID25mV
FB
VSEN
COMP
VCC
PWM2
ISEN2
MAIN
CONTROL
ISL6553
PWM1
FS/DIS
GND
ISEN1
+12V
BOOT
PVCC
VCC
PWM
DRIVER
HIP6601
UGATE
PHASE
LGATE
GND
VIN = +5V
3

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ISL6553
Typical Application - Two Phase Converter Using an HIP6602 Gate Driver
+5V
PGOOD
VID3
VID2
VID1
VID0
VID25mV
FB
VSEN
COMP
VCC
ISEN1
PWM1
MAIN
CONTROL
ISL6553
FS/DIS
PWM2
ISEN2
GND
+12V
VCC
BOOT1 VIN = +12V
UGATE1
PHASE1
PWM1
LGATE1
DUAL
DRIVER
HIP6602
PVCC
+5V
BOOT2
VIN +12V
PWM2
UGATE2
PHASE2
LGATE2
GND
L01
L02
+VCORE
4

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ISL6553
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . GND -0.3V to VVCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT SUPPLY POWER
Input Supply Current
POR (Power-On Reset) Threshold
RT = 100k, Active and Disabled Maximum Limit
VCC Rising
- 10
4.25 4.38
15
4.5
mA
V
VCC Falling
3.75 3.88 4.00 V
REFERENCE AND DAC
DAC Voltage Accuracy
DAC Pin Input Low Voltage Threshold
-1 - 1 %
- - 0.8 V
DAC Pin Input High Voltage Threshold
2.0 - - V
VID Pull-Up
OSCILLATOR
VIDx = 0V or VIDx = 3V
10 20 40 A
Frequency, FSW
Adjustment Range
RT = 100k, 1%
See Figure 10
245 275 305 kHz
0.05 -
1.5 MHz
Disable Voltage
ERROR AMPLIFIER
Maximum Voltage at FS/DIS to Disable Controller. IFS/DIS = 1mA
-
- 1.0 V
DC Gain
Gain-Bandwidth Product
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
ISEN
RL = 10K to GND
CL = 100pF, RL = 10K to GND
CL = 100pF, Load = 400A
RL = 10K to GND, Load = 400A
RL = 10K to GND, Load = -400A
- 72 - dB
- 18 - MHz
- 5.3 - V/s
3.6 4.1
-
V
- 0.16 0.5
V
Full Scale Input Current
Over-Current Trip Level
POWER GOOD MONITOR
Under-Voltage Threshold
Under-Voltage Threshold
PGOOD Low Output Voltage
PROTECTION
VSEN Rising
VSEN Falling
IPGOOD = 4mA
- 50 -
- 82.5 -
A
A
- 0.92 - VDAC
- 0.90 - VDAC
- 0.18 0.4
V
Over-Voltage Threshold
Percent Over-Voltage Hysteresis
VSEN Rising
VSEN Falling after Over-Voltage
1.12 1.15 1.2 VDAC
-2-%
5