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K4S281633D-RL(N)
Preliminary
CMOS SDRAM
8Mx16
SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V & 3.3V/3.3V)
Revision 0.6
November 2001
Rev. 0.6 Nov. 2001

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K4S281633D-RL(N)
Preliminary
CMOS SDRAM
Revision History
Revision 0.0 (February 21. 2001, Target)
• First generation of 128Mb Low Power SDRAM without special function (VDD 3.0V, VDDQ 3.0V)
Revision 0.1 (June 4. 2001, Target)
•Addition of DC Current value.
Revision 0.2 (June 20. 2001, Target)
•Changed device name from low power sdram to mobile dram.
Revision 0.3 (August 1. 2001, Target)
•Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part.
•Change of tOH from 3ns to 3.5ns.
•Change V IH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ.
Revision 0.4 (October 6. 2001, Preliminary)
•Changed DC current.
• Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part.
• Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part.
•Changed of tOH from 3ns to 2.5ns.
•Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part.
•Integration of VDDQ 1.8V device and 2.5V device.
•Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ.
•Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V.
•Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA.
•Erased -15 bin and added -1H bin.
Revision 0.5 (October 12. 2001, Preliminary)
•Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V.
•Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V.
Revision 0.6 (November 7. 2001, Preliminary)
•Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V.
Rev. 0.6 Nov. 2001

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K4S281633D-RL(N)
2M x 16Bit x 4 Banks SDRAM in 54CSP
Preliminary
CMOS SDRAM
FEATURES
• 3.0V & 3.3V power supply.
• LVTTL compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation..
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70 °C).
Extended Temperature Operation (-25°C ~ 85°C).
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S281633D is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNGs high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq. Interface Package
K4S281633D-RL/N75
133MHz(CL=3)
100MHz(CL=2)
K4S281633D-RL/N1H 100MHz(CL=2)
K4S281633D-RL/N1L 100MHz(CL=3)*1
LVTTL
54 CSP
-RN ; Low Power, Operating Temperature : -25’C~85’C.
-RL ; Low Power, Operating Temperature : -25’C~70’C.
Note : 1. In case of 40MHz Frequency, CL1 can be supported.
Data Input Register
CLK
ADD
Bank Select
2M x 16
2M x 16
2M x 16
2M x 16
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE LDQM UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.6 Nov. 2001

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K4S281633D-RL(N)
Preliminary
CMOS SDRAM
Package Dimension and Pin Configuration
< Bottom View*1 >
< Top View*2 >
E1
987 6 54 3 21
A
B
C
D
E
F
G
H
J
54Ball(6x9) CSP
123789
A VSS DQ15 VSSQ VDDQ DQ0 VD D
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 N C VSS VD D LDQM DQ7
F UDQM CLK CKE CAS RAS WE
G NC A11 A9 BA0 BA1 CS
H A8 A7 A6 A0 A1 A10
J
VSS
A5
A4
A3
A2 VD D
E
E/2
*2: Top View
Max. 0.20
Encapsulant
A
A1
ϕb ζ
*1: Bottom View
< Top View*2 >
#A1 Ball Origin Indicator
Pin Name
CLK
CS
CKE
A0 ~ A 11
BA0 ~ BA1
RAS
CAS
WE
L(U)DQM
DQ 0 ~ 15
VDD /VSS
V D D Q / VS S Q
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
Symbol
Min
Typ
Max
A 0.90 0.95 1.00
A1 0.30 0.35 0.40
E - 8.00 -
E1 - 6.40 -
D - 8.00 -
D1 - 6.40 -
e - 0.80 -
ϕb 0.40 0.45 0.50
ζ - - 0.08
Rev. 0.6 Nov. 2001

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K4S281633D-RL(N)
Preliminary
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VD D supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VI N, VOUT
VDD , VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA =-25°C ~ 70 °C (Commercial), -25 °C ~ 85°C (Extended))
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
VD D
VDDQ
VI H
VIL
VO H
VOL
IL I
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ Max Unit
3.0 3.6
V
3.0 3.6
V
3.0 VDDQ+0.3
V
0 0.5 V
- -V
- 0.4 V
- 10 uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
Note : 1. VIH (max) = 5.3V AC. The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE (VDD = 3.0V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
D Q0 ~ D Q15
Symbol
CCLK
CIN
CADD
COUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
Rev. 0.6 Nov. 2001