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K4S560832B
CMOS SDRAM
256Mbit SDRAM
8M x 8bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.2
May. 2000
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.2 May.2000

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K4S560832B
Revision 0.1 (March 10, 2000)
• Deleted -80 Product Specification
• Changed the Current values of ICC5, ICC6
• Changed tOH of -75 Product from 2.7ns to 3ns
• Changed the Bank select address in SIMPLIFIED TRUTH TABLE Notes 4.
BA0
Low
Low
High
High
BA1
Low
High
Low
High
Before
Bank A
Bank B
Bank C
Bank D
After
Bank A
Bank C
Bank B
Bank D
Revision 0.2 (May 30, 2000)
• Eliminate "Preliminary"
• Add "133MHz" in IBIS SPECIFICATION
CMOS SDRAM
Rev. 0.2 May.2000

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K4S560832B
8M x 8Bit x 4 Banks Synchronous DRAM
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S560832B is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 8,392,608 words by 8 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
Part No.
K4S560832B-TC/L75
K4S560832B-TC/L1H
K4S560832B-TC/L1L
Max Freq. Interface Package
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
54pin
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Data Input Register
CLK
ADD
Bank Select
8M x 8
8M x 8
8M x 8
8M x 8
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK CKE CS RAS CAS WE DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.2 May.2000

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K4S560832B
PIN CONFIGURATION (Top view)
CMOS SDRAM
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ7
52 VSSQ
51 N.C
50 DQ6
49 VDDQ
48 N.C
47 DQ5
46 VSSQ
45 N.C
44 DQ4
43 VDDQ
42 N.C
41 VSS
40 N.C/RFU
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitcH)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS Chip select
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE Write enable
DQM
Data input/output mask
DQ0 ~7
VDD/VSS
VDDQ/VSSQ
Data input/output
Power supply/ground
Data output power/ground
N.C/RFU
No connection
/reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Rev. 0.2 May.2000

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K4S560832B
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
VDD, VDDQ
VIH
VIL
VOH
VOL
ILI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ Max Unit
3.3 3.6
V
3.0 VDD+0.3
V
0 0.8 V
- -V
- 0.4 V
- 10 uA
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Note
1
2
IOH = -2mA
IOL = 2mA
3
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ0 ~ DQ15
Symbol
CCLK
CIN
CADD
COUT
Min
2.5
2.5
2.5
4.0
Notes : 1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
Rev. 0.2 May.2000