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Preliminary
256K
X84256
µPort Saver EEPROM
MPSEEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—2.5V–5.5V and 5V ±10% Versions
—Standby Current Less than 1µA
—Active Current Less than 3mA
• Byte or Page Write Capable
—64-Byte Page Write Mode
• Typical Nonvolatile Write Cycle Time: 2ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Packages Options
—8, 16-Lead SOIC Packages
—14-Lead TSSOP Packages
—8-Lead XBGA Packages
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
The µPort Saver memory outputs data within 25ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to 10
MHz, the µPort Saver supplies data faster than required
by most host read cycle specifications. This eliminates
the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Ports
Saved
µP
µC
DSP
ASIC
RISC
P0/CS
P1/CLK
P2/DI
P3/DO
A15
A0
D7
D0
OE
WE
Internal Block Diagram
MPS
WP H.V. GENERATION
TIMING & CONTROL
CE
COMMAND
I/O DECODE
OE
AND
CONTROL
LOGIC
WE
X
DEC
EEPROM
ARRAY
32K x 8
Y DECODE
DATA REGISTER
©Xicor, Inc. 1998 Patents Pending
4005 1 8/24/99 WW
1 Characteristics subject to change without notice

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X84256
Preliminary
PIN CONFIGURATIONS
Drawings are to the same scale, actual package sizes are
shown in inches:
CE
I/O
WP
VSS
8-LEAD SOIC
18
27
36
45
VCC
NC
OE
WE
CE
I/O
NC
NC
NC
WP
VSS
14-LEAD TSSOP
1 14
2 13
3 12
4 11
5 10
69
78
V CC
NC
NC
NC
NC
OE
WE
VCC
NC
WE
OE
8-LEAD XBGA
18
2 X84256 7
36
45
I/O
CE
VSS
WP
16-LEAD SOIC
CE
I/O
NC
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
NC
NC
NC
NC
NC
OE
WE
PIN NAMES
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
VCC Supply Voltage
VSS Ground
NC No Connect
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes to
the device are disabled. When WP is HIGH, all functions,
including nonvolatile writes, operate normally. If a nonvol-
atile write cycle is in progress, WP going LOW will have
no effect on the cycle already underway, but will inhibit
any additional nonvolatile write cycles.
DEVICE OPERATION
The X84256 serial EEPROM is designed to interface
directly with most microprocessor buses. Standard CE,
OE, and WE signals control the read and write opera-
tions, and a single l/O line is used to send and receive
data and commands serially.
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X84256
Data Timing
Data input on the l/O line is latched on the rising edge of
either WE or CE, whichever occurs first. Data output on
the l/O line is active whenever both OE and CE are LOW.
Care should be taken to ensure that WE and OE are
never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and CE
LOW, OE HIGH) to the part without a read cycle between
the write cycles. The address is sent serially, most signifi-
cant bit first, over the I/O line. Note that this sequence is
fully static, with no special timing restrictions, and the
processor is free to perform other tasks on the bus when-
ever the device CE pin is HIGH. Once the 16 address
bits are sent, a byte of data can be read on the I/O line by
issuing 8 separate read cycles (OE and CE LOW, WE
HIGH). At this point, writing a ‘1’ will terminate the read
sequence and enter the low power standby state, other-
wise the device will await further reads in the sequential
read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read. The
data stored in the memory at the next address can be
read sequentially by continuing to issue read cycles.
When the highest address in the array is reached, the
address counter rolls over to address $0000 and reading
may be continued indefinitely.
Preliminary
Reset Sequence
The reset sequence resets the device and sets an inter-
nal write enable latch. A reset sequence can be sent at
any time by performing a read/write “0”/read operation
(see Figs. 1 and 2). This breaks the multiple read or write
cycle sequences that are normally used to read from or
write to the part. The reset sequence can be used at any
time to interrupt or end a sequential read or page load.
As soon as the write “0” cycle is complete, the part is
reset (unless a nonvolatile write cycle is in progress). The
second read cycle in this sequence, and any further read
cycles, will read a HIGH on the l/O pin until a valid read
sequence (which includes the address) is issued. The
reset sequence must be issued at the beginning of both
read and write sequences to be sure the device initiates
these operations properly.
Write Sequence
A nonvolatile write sequence consists of sending a reset
sequence, a 16-bit address, up to 64 bytes of data, and
then a special “start nonvolatile write cycle” command
sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write enable
latch. The address is written serially by issuing 16
separate write cycles (WE and CE LOW, OE HIGH) to
the part without any read cycles between the writes. The
address is sent serially, most significant bit first, on the
l/O pin. Up to 64 bytes of data are written by issuing a
multiple of 8 write cycles. Again, no read cycles are
allowed between writes.
CE
OE
WE
I/O (IN)
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
RESET
WHEN ACCESSING: X84256 ARRAY: A15=0
LOAD ADDRESS
Figure 1. Read Sequence
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D7 D6 D5 D4 D3 D2 D1 D0
READ DATA

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X84256
Preliminary
CE
OE
WE
I/O (IN)
I/O (OUT)
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
RESET
WHEN ACCESSING: X84256 ARRAY: A15=0
LOAD ADDRESS
LOAD DATA
START
NONVOLATILE
WRITE
Figure 2. Write Sequence
The nonvolatile write cycle is initiated by issuing a special
read/write “1”/read sequence. The first read cycle ends
the page load, then the write “1” followed by a read starts
the nonvolatile write cycle. The device recognizes 64-
byte pages (e.g., beginning at addresses XXXXXXXXX
000000 for X84256).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this reason,
sending more than 512 consecutive data bits will result in
overwriting previous data.
result: I/O is LOW as long as a nonvolatile write cycle is
in progress, and l/O is HIGH when the nonvolatile write
cycle is done.
Low Power Operation
The device enters an idle state, which draws minimal
current when:
• an illegal sequence is entered. The following are the
more common illegal sequences:
—Read/Write/Write—any time
—Read/Write ‘1’—When writing the address or writ-
ing data.
A nonvolatile write cycle will not start if a partial or incom-
plete write sequence is issued. The internal write enable
latch is reset when the nonvolatile write cycle is com-
pleted and after an invalid write to prevent inadvertent
writes. Note that this sequence is fully static, with no spe-
cial timing restrictions. The processor is free to perform
other tasks on the bus whenever the chip enable pin
(CE) is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined
at any time by simply reading the state of the l/O pin on
the device. This pin is read when OE and CE are LOW
and WE is HIGH. During a nonvolatile write cycle the l/O
pin is LOW. When the nonvolatile write cycle is complete,
the l/O pin goes HIGH. A reset sequence can also be
issued during a nonvolatile write cycle with the same
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
May change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW to
HIGH
Will change
from HIGH to
LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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X84256
Preliminary
—Write ‘1’—when reading data
—Read/Read/Write ‘1’—after data is written to device,
but before entering the NV write sequence.
—the device powers-up;
—a nonvolatile write operation completes.
While a sequential read is in progress, the device remains
in an active state. This state draws more current than the
idle state, but not as much as during a read itself. To go
back to the lowest power condition, an invalid condition is
created by writing a ‘1’ after the last bit of a read operation.
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
—A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias ...................... –65°C to +135°C
Storage Temperature ........................... –65°C to +150°C
Terminal Voltage with
Respect to VSS .......................................–1V to +7V
DC Output Current................................................... 5mA
Lead Temperature (Soldering, 10 seconds)..........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military†
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Supply Voltage
X84256
X84256 – 2.5
X84256 – 1.8
Limits
5V ±10%
2.5V to 5.5V
1.8V to 3.6V
D.C. OPERATING CHARACTERISTICS (VCC = 5V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Symbol
Parameter
Limits
Min.
Max.
Units
Test Conditions
ICC1
VCC Supply Current (Read)
ICC2
ISB1
ILI
ILO
VlL (1)
VIH (1)
VOL
VOH
VCC Supply Current (Write)
VCC Standby Current
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
1
3
–0.5
VCC x 0.7
VCC – 0.8
1
10
10
VCC x 0.3
VCC + 0.5
0.4
mA OE = VIL, WE = VIH,
I/O = Open, CE clocking @ 10MHz
mA
ICC During Nonvolatile Write Cycle
All Inputs at CMOS Levels
µA CE = VCC, Other Inputs = VCC or VSS
µA VIN = VSS to VCC
µA VOUT = VSS to VCC
V
V
V IOL = 2.1mA
V IOH = –1mA
Notes: (1) VIL Min. and VIH Max. are for reference only and are not tested.
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