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Preliminary Information
XZ8®6CM6ic4rocontroller Family Compatible
64K X86C64
E2 Micro-Peripheral
8192 x 8 Bit
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200 µA Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
DESCRIPTION
The X86C64 is an 8K x 8 E2PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
FUNCTIONAL DIAGRAM
CE
R/W
DS
SEL
A8–A11
AS
CONTROL
LOGIC
LX
AD
TE
CC
HO
ED
SE
WC
A12
SOFTWARE
DATA
PROTECT
A12
1K BYTES A12 1K BYTES
M
1K BYTES
1K BYTES
U
1K BYTES X 1K BYTES
1K BYTES
1K BYTES
Y DECODE
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITEis a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3819 FHD F02
1 Characteristics subject to change without notice

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X86C64
PIN DESCRIPTIONS
Address/Data (A/D0–A/D7)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is LOW. After AS
transitions from a LOW to HIGH the addresses are
latched. Once the addresses are latched these pins input
data or output data depending on DS, R/W, and CE.
Addresses (A8–A12)
High order addresses flow into the device when AS = VIL
and are latched when AS goes HIGH.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and AS is HIGH, the
X86C64 is placed in the low power standby mode.
Data Strobe (DS)
When used with a Z8 the DS input is tied directly to the
DS output of the microcontroller.
Read/Write (R/W)
When used with a Z8 the R/W input is tied directly to the
R/W output of the microcontroller.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is LOW and are latched when AS transitions
from a LOW to HIGH.
Device Select (SEL)
Must be connected to VSS.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or proces-
sor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E2PROM. If the
Write Control input is driven HIGH (before tTBLC Max)
after Read/Write (R/W) goes HIGH, the write cycle will
be aborted.
When WC is LOW (tied to VSS) the X86C64 will be
enabled to perform write operations. When WC is HIGH
normal read operations may be performed, but all at-
tempts to write to the device will be disabled.
PIN CONFIGURATION
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
DIP/SOIC
1 24
2 23
3 22
4 21
5 20
6 19
X86C64
7 18
8 17
9 16
10 15
11 14
12 13
VCC
R/W
AS
A8
A9
A11
DS
A10
CE
A/D7
A/D6
A/D5
3819 FHD F01
PIN NAMES
Symbol
AS
A/D0–A/D7
A8–A12
DS
R/W
CE
WC
SEL
VSS
VCC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Data Strobe Input
Read/Write Input
Chip Enable
Write Control
Device Select—Connect to VSS
Ground
Supply Voltage
3819 PGM T01
2

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X86C64
PRINCIPLES OF OPERATION
The X86C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X86C64 provides 8K bytes of 5-volt E2PROM which can
be used either for Program Storage, Data Storage or a
combination of both in systems based upon Von
Neumann (86XX) architectures. The X86C64 incorpo-
rates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “ Seamless” interface.
The interface inputs on the X86C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X86C64 is internally organized as two independent
planes of 4K bytes of memory with the A12 input select-
ing which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X86C64 during a byte or page write to the
device.
The X86C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sec-
tions can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up con-
figuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X86C64 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X86C64 also features the industry standard 5-volt
E2PROM characteristics such a byte or page mode write
and toggle-bit polling.
DEVICE OPERATION
Zilog Z8 operation requires the microcontroller’s AS, DS
and R/W outputs tied to the X86C64 AS, DS and
R/W inputs respectively.
The rising edge of AS will latch the addresses for both a
read and write operation. The state of R/W output
determines the operation to be performed, with the DS
signal acting as a data strobe.
If R/W is HIGH and CE HIGH (read operation) data will
be output on A/D0–A/D7 after DS transitions LOW. If
R/W is LOW and CE is HIGH (write operation) data
presented at A/D0–A/D7 will be strobed into the X86C64
on the LOW to HIGH transition of DS.
Typical Application
2 XTAL
3 EXTAL
21
P10
22
P11
23
P12
24
P13
25
P14
26
P15
27
P16
28
P17
13
P00
14
P01
15
P02
16
P03
17
P04
20
P07
9
AS
8
DS
7
R/W
Z8
24
7
A/D0
8
A/D1
9
A/D2
10
A/D3
11
A/D4
13
A/D5
14
A/D6
15
A/D7
21
A8
20
A9
17
A10
19
A11
2
A12
16
CE
5
WC
22
AS
18
DS
23
R/W
6
SEL
VCC
VSS
X86C64
12
3819 FHD F03
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X86C64
MODE SELECTION
CE DS
VSS X
VIL X
VIH VIL
VIH
R/W
X
X
VIH
VIL
Mode
Standby
Standby
Read
Write
I/O
High Z
High Z
DOUT
DIN
Power
Standby (CMOS)
Standby (TTL)
Active
Active
3819 PGM T08
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X86C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X86C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of DS starts a timer
delaying the internal programming cycle 100 µs. There-
fore, each successive write operation must begin within
100 µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for DS Controlled Operation
OPERATION
CE
AS
A/D0–A/D7
A8–A12
DS
BYTE 0
AIN DIN
A12=n
BYTE 1
AIN DIN
A12=n
BYTE 2
LAST BYTE
READ (1)(2)
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=x
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN
ADDR
AIN
Next Address
R/W
tBLC
tWC
381398F1H9DFFH07D F07
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A12 of Read A12 of Write) true data will be returned, facilitating the use of a
single memory component as both program and data store.
4

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X86C64
Toggle Bit Polling
Because the X86C64 typical write timing is less than the
specified 5 ms, Toggle Bit Polling has been provided to
determine the early end of write. During the internal
programming cycle I/O6 will toggle from one to zero and
zero to one on subsequent attempts to read the device.
Toggle Bit Polling DS Control
When the internal cycle is complete the toggling will
cease and the device will be accessible for additional
read or write operations. Due to the dual plane architec-
ture, reads for polling must occur in the plane that was
written; that is, the state of A12 during write must match
the state of A12 during polling.
OPERATION
CE
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C64 READY FOR
NEXT OPERATION
AS
A/D0–A/D7
AIN DIN
AIN DOUT
AIN DOUT
AIN DOUT
AIN DOUT
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=n
ADDR
DS
R/W
3819 FHD F08
5