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APPLICATION NOTE
A V A I LABLE
Application Brief
iAPX88/188, MCS 196, MCS51 Compatible*
64K
X88064
8192 x 8 Bit
E2 Microcontroller Peripheral
• Block Lock Write Control
—Eight 1K Byte Blocks
- Lockable Independently or in Combination
• Multiplexed Address/Data Bus
—Direct Interface to Popular Microcontrollers
• High Performance CMOS
—Fast Access Times, 60ns and 80 ns
—Low Power
- 30mA Active Maximum
- 150µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
DESCRIPTION
The X88064 is a high speed byte wide microperipheral
device with eight 1K byte blocks of E2PROM and can be
directly connected to industry standard high performance
microprocessors. This peripheral provides two levels of
memory write control, the standard Software Data Pro-
gram (SDP) control and Block Lock.
Block Lock provides a higher level of memory write con-
trol above SDP. This allows the software developer to
partition any or all of the eight 1K byte blocks as In-Circuit
Programmable ROM (ICPROM). Once locked, a block of
memory must first be unlocked before being written. Not
even a write operation using the SDP sequence will
change the contents of a locked block. Since a distinct, 6
byte, software command sequence locks and unlocks
the memory, the software developer has complete con-
trol of the memory contents.
ALE
A/D0–A/D7
A8–A12
L
A
T
C
H
WR
RD
PSEN
CE
WC
INTERFACE
CONTROL
BLOCK LOCK
CONTROL
LOGIC
D
E
C
O
D
E
R
INDIVIDUALLY LOCKABLE
E2 PROM
ARRAY
1Kx8 BLOCKS
SOFTWARE DATA PROTECT
(SDP)
WE
OE BUS TRANSCEIVER
POWER-ON RESET
AND VCC SENSE
A/D0–A/D7
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
* All other brand and product names may be trademarks or
registered trademarks of their respective companies.
7023-2.3 1/29/97 T0/C2/D0 SH
1
Characteristics subject to change without notice

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X88064
Software Data Program Control provides a lower level of
memory write management. SDP controls write opera-
tions to the entire memory. When enabled, the host micro-
processor must send a special 3 byte command sequence
before any byte or page writes to unlocked locations in the
memory.
Pin configuration
DIP/SOIC
NC
A12
NC
NC
WC
PSEN
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 24
2 23
3 22
4 21
5 20
6 X88064 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
WR
ALE
A8
A9
A11
RD
A10
CE
A/D7
A/D6
A/D5
7023 FRM F02
PIN NAMES
PIN NAME
PSEN
A8–A12
AD0–AD7
WR
RD
WC
CE
ALE
I/O DESCRIPTION
I Content of E2 memory can be read by lowering the PSEN and holding both RD and WR
HIGH. The device then places on the data bus (AD0–AD7) the contents of E2 memory at the
latched address.
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a
HIGH to LOW transition.
I During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is
placed on the bus. The rising edge of WR latches data into the device.
I The RD input is active LOW and is used to read content of the E2 memory at the latched
address. Both PSEN an WR signals must be held HIGH during RD controlled read operation.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order
to disable write to the E2 memory. Taking WC HIGH prior to tBLC (100ns, the time delay from
the last write cycle to the start of internal programming cycle) will inhibit the write operation.
I The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE
HIGH to LOW transition in order to generate a valid internal device select signal. Holding this
pin HIGH and ALE LOW will place the device in standby mode.
I Address Latch Enable input is used to latch the addresses present on the address lines
A8–A12 and AD0–AD7 into the device. The addresses are latched when ALE transitions from
HIGH to LOW.
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X88064
PRINCIPLES OF OPERATION
The X88064 is a highly integrated peripheral device for a
wide variety of single-chip microcontrollers. The X88064
provides 8K bytes of E2PROM which can be used either
for Program Storage, Data Storage, or a combination of
both, in systems based upon Harvard (80XX) architec-
tures. The X88064 incorporates the interface circuitry
normally needed to decode the control signals and
demultiplex the Address/Data bus to provide a “Seam-
less” interface.
The interface inputs on the X88064 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip microcon-
troller. In the Harvard type system, the reading of data
from the chip is controlled either by the PSEN or the RD
signal, which essentially maps the X88064 into both the
Program and the Data Memory address map.
The X88064 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock, which allows the device to be broken into 8 inde-
pendent sections of 1K bytes. Each of these sections can
be independently enabled for write operations; thereby
allowing certain sections of the device to be secured so
that updates can only occur in a controlled environment
(e.g. in an automotive application, only at an authorized
service center). The desired set-up configuration is
stored in a nonvolatile register, ensuring the configuration
data will be maintained after the device is powered down.
The X88064 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X88064 also features the industry standard
E2PROM characteristics such as byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION MODES
Mixed Program/Data Memory
By properly assigning the address space, a single
X88064 can be used as both the Program and Data
Memory. This would be accomplished by connecting all
of the Microcontroller control outputs to the correspond-
ing inputs of the X88064.
The Data Storage can be fully protected by enabling
Block Lock Control.
Program Memory Mode
This mode of operation is read-only. The PSEN and ALE
inputs of the X88064 are tied directly to the PSEN and
ALE outputs of the microcontroller. The RD and WR
inputs are tied HIGH.
When ALE is HIGH, the A/D0–A/D7 and A8–A12
addresses flow into the device. The addresses, both low
and high order, are latched when ALE transitions LOW
(VIL). PSEN will then go LOW and after tPLDV, valid data
is presented on the A/D0–A/D7 pins. CE must be LOW
during the entire operation.
Data Memory Mode
This mode of operation allows both read and write func-
tions. The PSEN input is tied to VIH or to VCC through a
pull-up resistor. The ALE, RD, and WR inputs are tied
directly to the microcontroller’s ALE, RD, and WR out-
puts.
Read
This operation is quite similar to the Program Memory
read. A HIGH to LOW transition on ALE latches the
addresses and the data will be output on the A/D pins
after RD goes LOW (tRLDV).
Write
A write is performed by latching the addresses on the fall-
ing edge of ALE. Then WR is strobed LOW followed by
valid data being presented at the A/D0–A/D7 pins. The
data will be latched into the X88064 on the rising edge of
WR. To write to the X88064, with the SDP feature
enabled, a three-byte command sequence must precede
the byte(s) being written. (See Software Data Protec-
tion.)
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X88064
MODE SELECTION
CE
VCC
HIGH
LOW
PSEN
X
X
LOW
LOW
HIGH
LOW
HIGH
RD
X
X
HIGH
LOW
HIGH
WR
X
X
HIGH
HIGH
Mode
Standby
Standby
Program Fetch
Data Read
Write
I/O
High Z
High Z
DOUT
DOUT
DIN
TYPICAL APPLICATIONS
U4
LATCH
U3
RAM
U2
LCS
A/D0A/D7
X1 A/D8A/D15
X2
UCS
ALE/QS0
WR/QS1
RD/QSMD
80188
U1
A/D0A/D7
A8A12
WC
PSEN
CE
ALE
WR
RD
X88064
188 Interface
VCC
EA/VP A/D0A/D7
X1
A8A12
X2
PSEN
ALE
RD
WR
P2.7
80C51 µC Family
Power
Standby (CMOS)
Standby (TTL)
Active
Active
Active
7023 FRM T02
VCC
A/D0A/D7
A8A12
WC
PSEN
ALE
RD
WR
CE
X88064
U2
X1 A/D0A/D7
A/D8A/D15
X2
EA
ALE
BUSWIDTH WR
RD
8X196 KC/KD
U1
A/D0A/D7
A8A12 WC
PSEN
CE
ALE
WR
RD
X88064
VCC
196 Interface
4
7023 FRM F03

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X88064
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X88064
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X88064. Each individual write within a page
write operation must conform to the byte write timing
requirements. The falling edge of WR starts a timer
delaying the internal programming cycle 100µs. There-
fore, each successive write operation must begin within
100µs of the last byte written. The following waveforms
illustrate the sequence and timing requirements.
Page Write Timing Sequence for WR Controller Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
CE
ALE
A/D0 –A/D 7
A8 –A12
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
WR
READ (1)
AIN DOUT
A12=x
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN
ADDR
AIN
Next Address
PSEN(RD)
tBLC
Notes: (1) For each successive write within a page write cycle A5–A12 must be the same.
tWC
7023 FRM F04
5