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APPLICATION NOTES
AVA I L A B L E
X88C75ASN6L2 •ICAN®64E• A2N66
SLIC X88C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between Planes
• Allows Continuous Execution Of Code From
One Plane While Writing In The Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 80C51 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X88C75 SLIC is a highly integrated peripheral for
the 80C51 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
two bidirectional 8-bit ports, 16 general purpose regis-
ters, programmable internal address decoding and a
multiplexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-bytes
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
PIN CONFIGURATIONS
DIP
RESET
A12
WC
PSEN
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
X88C75
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2887-2.5 4/11/97 T0/C0/D1 SH
VCC
WR
ALE
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
RD
A10
CE
A/D7
A/D6
A/D5
28288787ILILLLF0F101
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X88C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2887 ILL F02.4
Concurrent Read During Write, Block Lock, and
SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice

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X88C75 SLIC® E2
which allows Individual blocks of the memory to be
configured as read-only or read/write.
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X88C75 is accomplished through the
multiplexed address/data bus of the 80C51 type control-
lers. An internal programmable address decoder maps
the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X88C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X88C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 80C51 microcontroller. The
reading of data from the chip is controlled either by the
PSEN or the RD signal, which essentially maps the
X88C75 into both the Program and the Data Memory
address map.
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
ALE latches the address to be written into the X88C75.
The rising edge of WR latches the data to be written.
The nonvolatile memory of the X88C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X88C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X88C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock Protect, which allows the nonvolatile memory array
to be treated as 8 independent sections of 1K-bytes.
Each of these sections can be independently enabled
for write operations. This allows segmentation of the
memory contents into writable and non-writable sec-
tions, thereby, allowing certain sections of the device to
be secured so that updates can only occur in a controlled
environment. (e.g. in an automotive application, only at
FUNCTIONAL DIAGRAM
A0–A15
ADDRESS
LATCH
I/O0–I/O7
I/O
BUFFER
&
LATCH
CE
WR
RD
ALE
PSEN
WC
RESET
IRQ
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
DATA I/O BUS
RIGHT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
16 X 8
GENERAL
PURPOSE
REGISTERS
PORT SELECT
PORT
A
PORT
B
SDP
DECODE
MEM. MAP
CONFIG
REGISTER
PORT
SPECIAL
FUNCTION
REGISTERS
2887 ILL F03
2

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X88C75 SLIC® E2
an authorized service center). The Block Protect con-
figuration is stored in a nonvolatile register, ensuring
that the configuration data will be maintained after the
device is powered-down.
The X88C75 write control input, serves as an external
control over the completion of a previously initiated page
load cycle.
The X88C75 also features the industry standard 5V E2
memory characteristics such as byte or page mode write
and Toggle Bit Polling.
Read
A HIGH to LOW transition on ALE latches the address;
the data will be output on the AD pins after either RD or
PSEN goes LOW (tRDLV).
Write
A write is performed by latching the addresses on the
falling edge of ALE. The WR is strobed LOW followed by
valid data being presented on the AD0–AD7 pins. The
data will be latched into the X88C75 on the rising edge
of WR.
Page Write Operation
The X88C75 supports page mode write operations. This
allows the microcontroller to write from one to thirty-two
bytes of data to the X88C75. Each individual write within
a page write operation must conform to the byte write
timing requirements. The falling edge of WR starts a
timer delaying the internal programming cycle 100µs:
therefore, each successive write operation must begin
within 100µs of the last byte written. The waveform
on page 4 illustrates the sequence and timing
requirements.
PIN DESCRIPTIONS
PIN NAME
RESET
PSEN
STRA, STRB
PA7–PA0
PB7–PB0
A15–A8
AD7–AD0
WR
RD
IRQ
WC
CE
ALE
I/O DESCRIPTION
I RESET is used to initialize the internal static registers and has no effect on the E2 memory opera-
tions. The default active level is HIGH, but it can be reconfigured in EEM register.
I Content of E2 memory can be read by lowering the PSEN and holding both RD and WR HIGH. The
device then places on the data bus (AD7–AD0) the contents of E2 memory at the latched address.
I/O The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid
transition on their strobe pins will latch into their port data register the data present at the port input
pins. Writing to an output port data register generates a pulse of fixed duration on its corresponding
strobe pin. The output data presented at the output pins stay valid until the next data is written to the
output port data register.
I/O The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the
AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select port A I/O mode.
I/O The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the
BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select port B I/O mode.
I Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
I/O Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH
to LOW transition.
I During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is placed on
the Data Bus. The rising edge of WR will latch the data into the device.
I The RD input is active LOW and is used to read content of either the E2 memory or the SFR at the
latched address. Both PSEN and WR signals must be held HIGH during RD controlled read
operation.
O The IRQ is an open-drain output. It can be configured to signal latching of new data into any of the
ports, and/or completion of the E2 memory internal write cycle.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to
disable write to the E2 memory. Taking WC HIGH prior to tBLC (100µs, the time delay from the last
write cycle to the start of internal programming cycle) will inhibit the write operation.
I The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE HIGH to
LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and
ALE LOW will place the device in standby mode. The ports stay active at all times.
I Address Latch Enable input is used to latch the addresses present on the address lines A15–A8 and
AD7–AD0 into the device. The addresses are latched when ALE transitions from HIGH to LOW.
2887 PGM T01.1
3

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X88C75 SLIC® E2
Page Write Operation
OPERATION
BYTE 0
CE
ALE
A/D0–A/D7
A8–A12
AIN DIN
A12=n
WR
PSEN(RD)
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DOUT
A12=x
AIN
ADDR
AIN
Next Address
tBLC
tWC
2887 ILL F04
Toggle Bit Polling
Because the X88C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
determine the early completion of a write cycle. During
the internal programming cycle, I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
internal cycle is complete, the toggling will cease and
the device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A12 during a write must match the state
of A12 during polling.
Figure 1. Toggle Bit Polling
OPERATION
LAST BYTE
WRITTEN
CE
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X88C75 READY FOR
NEXT OPERATION
ALE
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=x
AIN
ADDR
WR
RD
2887 ILL F05
4

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X88C75 SLIC® E2
DATA PROTECTION
The X88C75 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Lock Protect write lockout
protection providing a secondary level data security
option.
Software Data Protection
Software Data Protection (SDP) can be employed to
protect the entire array against inadvertent writes during
power-up/power-down operations. The X88C75 is
shipped from the factory with SDP enabled. With SDP
enabled, inadvertent attempts to write to the X88C75 will
be blocked.
The system can still write data, but only when the write
operation (page or byte) is preceded by the three-byte
command sequence. All write operations, both the com-
mand sequence and any data write operations must
conform to the page write timing requirements.
The SDP mode is also enabled anytime one of the
nonvolatile configuration registers are modified. These
include writing to EE map, SFR map, and BPR.
Figure 2. Writing With SDP Enabled
AA b2 b1 b0 P 555
55 b2 b1 b0 P AAA
A0 b2 b1 b0 P 555
Perform Byte or
Page Write Operations
Delay of tWC
Exit Routine
2887 ILL F06
b2
b1
b0
Reference the A15–A13
setting in EEM register
P = Address bit (A12) of the
updated memory plane
Figure 3. Sequence to Deactivate Software Data
Protection
AA b2 b1 b0 P 555
55 b2 b1 b0 P AAA
A0 b2 b1 b0 P 555
AA b2 b1 b0 P 555
80 b2 b1 b0 P AAA
Delay of tWC
Exit Routine
2887 ILL F07
b2
b1
b0
Reference the A15–A13
setting in EEM register
P = Address bit (A12) of the
memory plane not being read.
Block Lock Protect Write Lockout
The X88C75 provides a second level of data security
referred to as Block Lock Protect write lockout (or Block
Protect). This is accessed through an extension of the
SDP command sequence. Block Protect allows the user
to lockout writes to 1K x 8 blocks of memory. Unlike SDP
which prevents inadvertent writes, but still allows easy
system access to writing the memory, Block Protect will
lockout all attempts unless it is specifically disabled by
issuing the deactivation sequence. This feature can be
used to set a higher level of protection in a system where
a portion of the memory is used to store the system
kernel and protect it from the application programs
residing in the other blocks.
Setting write lockout is accomplished by writing a five-
byte command sequence opening access to the Block
Protect Register (BPR). After the fifth byte is written, the
user writes to the BPR, selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements. It should be noted
5