X9111 – Preliminary Information
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
DEVICE ADDRESS (A0, A1)
The address inputs are used to set the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input (A1–A0)
in order to initiate communication with the X9111.
CHIP SELECT (CS)
When CS is HIGH, the X9111 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9111, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
The wiper pin is equivalent to the wiper terminal of a
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin
is the system ground.
NO CONNECT (NC)
Pin should be left open. This pin is used for Xicor
manufacturing and test purposes.
PRINCIPLES OF OPERATION
The X9111 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked-in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
The X9111 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 1023 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the ﬁxed
terminals of a mechanical potentiometer (RH and RL
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within the individual array only one switch
may be turned on at a time.
REV 1.1.15 5/9/03
Characteristics subject to change without notice. 4 of 21