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APPLICATION NOTES AND DEVELOPMENT SYSTEM
AVAILABLE
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / 2-Wire bus
X9259
Quad Digitally-Controlled (XDCPTM) Potentiometers
FEATURES
• Quad–Four separate potentiometers
• 256 resistor taps/pot–0.4% resolution
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100typical @ VCC = 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power Up.
• Standby Current < 5µA Max
• VCC: 2.7V to 5.5V Operation
• 50K, 100Kversions of End to End Pot
Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• Single Supply Version of X9258
• 24-Lead SOIC, 24-Lead TSSOP, 24-Lead XBGA
• Low Power CMOS
DESCRIPTION
The X9259 integrates 4 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default Data Register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power On Recall
Wiper Counter
Registers (WCR)
Data Registers
16 Bytes
RH0
RH1
RH2
RH3
VSS
RW0
RL0 RW1 RL1 RW2
RL2 RW3
RL3
50Kor 100Kversions
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X9259
DETAILED FUNCTIONAL DIAGRAM
SCL
SDA
A3
A2
A1
A0
WP
VCC
INTERFACE
AND
CONTROL
CIRCUITRY
8
Data
RH0 RL0 RW0
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
Pot 0
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
50Kand 100K
256-taps
Power On
Recall
DR0 DR1
DR2 DR3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VSS RL1 RH1 RW1
RH2
RL2
RW2
RW3
RH3
RL3
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment
systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
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X9259
PIN CONFIGURATION
SOIC/TSSOP
NC1
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
A2
WP
1 24
2 23
3 22
4 21
5 20
6 19
X9259
7 18
8 17
9 16
10 15
11 14
12 13
A3
SCL
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
A1
SDA
1
A RW0
RL0
B
VCC
C
NC
D
RL3
E
RW3
F
XBGA
23
A2 A1
WP SDA
RH0
RH3
RH1
RH2
NC1
A3
A0 SCL
4
RL1
RW1
VSS
NC
RW2
RL2
Top View–Bumps Down
PIN ASSIGNMENTS
Pin
(SOIC/TSSOP)
Pin
(XBGA)
Symbol
Function
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
1
F2
F1
D2
E1
E2
C1
B1
C2
A1
A2
B2
B3
A3
A4
C3
B4
C4
E4
D3
F4
F3
E3
D1, D4
E2
A0
RW3
RH3
RL3
NC1
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
VSS
RW2
RH2
RL2
SCL
A3
NC
NC1
Device Address for 2-Wire bus. (See Note 1)
Wiper Terminal for Potentiometer 3.
High Terminal for Potentiometer 3.
Low Terminal for Potentiometer 3.
Must be left unconnected
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for 2-Wire bus. (See Note 1)
Hardware Write Protect
Serial Data Input/Output for 2-Wire bus.
Device Address for 2-Wire bus. (See Note 1)
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
WiperTerminal for Potentiometer 2.
High Terminal for Potentiometer 2.
Low Terminal for Potentiometer 2.
Serial Clock for 2-Wire bus.
Device Address for 2-Wire Bus. (See Note 1)
No Connect
Must be left unconnected
Note 1: A0-A3 Device address pins must be tie to a logic level.
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X9259
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9259.
DEVICE ADDRESS (A3–A0)
The Address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9259. A maximum of 16 devices may occupy the
2-Wire serial bus. Device pins A3-A0 must be tie to a
logic level which specify the external address of the
device, see figures 3, 4, and 5.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of RH and
RL such that RH0 and RL0 are the terminals of POT 0
and so on.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4
potentiometers, there are 4 sets of RW such that RW0
is the terminal of POT 0 and so on.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin
is the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are used
for Xicor manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
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X9259
PRINCIPLES OF OPERATION
The X9259 is a integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description.
Array Description
The X9259 is comprised of a resistor array (see Figure
1). Each array contains 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
switch may be turned on at a time.
Figure 1. Detailed Potentiometer Block Diagram
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC VH,
VL, VW. The VCC ramp rate specification is always in
effect.
One of Four Potentiometers
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
REGISTER 2
(DR2)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
REGISTER 1
(DR1)
8
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
UP/DN
MODIFIED SCL
INC/DEC
LOGIC
UP/DN
CLK
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
RL
RW
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