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APPLICATION NOTE
AVA I L A B L E
X20C16 AN56
16K X20C16
High Speed AUTOSTORE™ NOVRAM
2K x 8 Bit
FEATURES
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
AUTOSTORE™ NOVRAM
—Automatically Stores RAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—User Enabled Option
—Open Drain AUTOSTORE Status Output Pin
Power-on Recall
—E2PROM Data Automatically Recalled Into
RAM Upon Power-up
Software Data Protection
—Locks Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250µA
Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28 VCC
2 27 WE
3 26 AS
4 25 A8
5 24 A9
6 23 NC
7 22
8 X20C16 21
9 20
10 19
11 18
12 17
13 16
14 15
OE
A10
CE
NC
OE
I/O7
I/O6
A9
A8
AS
I/O5 WE
I/O4
I/O3
VCC
NE
3826 FHD F02
NC
3826 FHD F15.1
A7
A6
A5
A4
A3
SOIC
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X20C16
8 21
9 20
10 19
11 18
12 17
13 16
14 15
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending
3826-2.9 7/31/97 T4/C0/D0 SH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
DESCRIPTION
The Xicor X20C16 is a 2K x 8 NOVRAM featuring a high-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E2PROM at power-down. The X20C16
is fabricated with advanced CMOS floating gate technol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C16 features a compat-
ible JEDEC approved pinout for byte-wide memories,
for industry standard RAMs, ROMs, EPROMs, and
E2PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
TSOP
LCC
PLCC
X20C16
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
A2 9
A1 10
X20C16
(TOP VIEW)
26 NC
25 OE
24 A10
A0 11
23 CE
3826 ILL F17.2
NC
I/O0
12 22
13 21
14 15 16 17 18 19 20
I/O7
I/O6
3826 FHD F03
Characteristics subject to change without notice
1

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X20C16
PIN DESCRIPTIONS
Addresses (A0–A10)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE, or NE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH or when NE is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to the
static RAM.
FUNCTIONAL DIAGRAM
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall function
to the E2PROM array.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
cates VCC has fallen below the AUTOSTORE threshold
(VASTH). AS may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller.
PIN NAMES
Symbol
A0–A10
I/O0–I/O7
WE
CE
OE
NE
AS
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
AUTOSTORE Output
+5V
Ground
No Connect
3826 PGM T01
AS VCC SENSE
EEPROM ARRAY
A3–A8
CE
OE
WE
NE
A0–A2
A9–A10
ROW
SELECT
CONTROL
LOGIC
HIGH SPEED
2K x 8
SRAM
ARRAY
COLUMN
SELECT
&
I/OS
I/O0–I/O7
3826 FHD F01
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X20C16
DEVICE OPERATION
The CE, OE, WE, and NE inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH, or
when NE is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW with WE and NE HIGH. A write
operation requires CE and WE to be LOW with NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C16.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E2PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E2PROM array.
Recall operations are performed automatically upon
power-up and under host system control when NE, OE
and CE are LOW and WE is HIGH. The recall operation
takes a maximum of 5µs.
SDP (Software Data Protection)
There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode: NE, CE, and WE strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step
operation: the first address/data combination is 555[H]/
AA[H]; the second combination is 2AA[H]/55[H]; and the
final command combination is 555[H]/33[H]. This se-
quence of pseudo write operations will immediately
initiate a store operation. Refer to the software com-
mand timing diagrams for details on set and hold times
for the various signals.
The second method of storing data is with the
AUTOSTORE command. When enabled, data is auto-
matically stored from the RAM into the E2PROM array
whenever VCC falls below the preset Autostore thresh-
old. This feature is enabled by performing the first two
steps for the software store with the command combina-
tion being 555[H]/CC[H].
The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com-
bination being 555[H]/CD[H]. The AUTOSTORE feature
will also be reset if VCC falls below the power-up reset
threshold (approximately 3.5V) and is then raised back
into the operation range.
Write Protection
The X20C16 supports two methods of protecting the
nonvolatile data.
—If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.
—VCC Sense – All functions are inhibited when VCC is
3.0V typical.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3