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X24001
128 Bit
FEATURES
2.7V to 5.5V Power Supply
128 Bit Serial E2PROM
Low Power CMOS
—Active Current Less Than 1mA
—Standby Current Less Than 50µA
Internally Organized 16 x 8
2 Wire Serial Interface
High Voltage Programmable Only
—VPGM, 12V to 15V
Push/Pull Output
High Reliability
—Data Retention: 100 Years
Available Packages
—8-Lead MSOP
—8-Lead PDIP
—8-Lead SOIC
X24001
IdentiPROM
16 x 8 Bit
DESCRIPTION
The X24001 is a CMOS 128 bit serial E2PROM, inter-
nally organized as 16 x 8. The X24001 features a serial
interface and software protocol allowing operation on a
simple two wire bus.
The X24001 is ideally suited for identification applica-
tions such as serial numbers or device revision numbers
which need to be stored and retrieved electronically.
VPGM is used to enable writes to the device. This
provides full protection of the data in the user’s environ-
ment where VPGM is not available.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
The X24001 is fabricated with Xicor’s Advanced CMOS
Floating Gate technology.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SCL
CONTROL
LOGIC
SDA
INPUT/
OUTPUT
BUFFER
COMMAND/ADDRESS
REGISTER
SHIFT REGISTER
MEMORY ARRAY
3830 FHD F01
MSOP/DIP/SOIC
NC
NC
NC
VSS
18
27
X24001
36
45
VCC
NC
SCL
SDA
3830 FHD F02.1
IDENTI™ PROM is a trademark of Xicor, Inc.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3830-1.5 6/10/96 T2/C1/D0 NS
1
Characteristics subject to change without notice

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X24001
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is a push/pull output and does not
require the use of a pull-up resistor. During the program-
ming operation, SDA is an input.
PIN NAMES
Symbol
NC
VSS
VCC
SDA
SCL
Description
No Connect
Ground
Supply Voltage
Serial Data
Serial Clock
3830 PGM T01
DEVICE OPERATION
The X24001 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. There-
fore, the X24001 will be considered a slave in all appli-
cations.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24001 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
A start may be issued to terminate the input of a control
word or the input of data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are also inhibited while a write is in progress.
Stop Condition
The stop condition is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is used to reset
the device during a command or data input sequence
and will leave the device in the standby mode. As with
starts, stops are inhibited when outputting data and
while a write is in progress.
2

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X24001
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
Figure 2. Definition of Start and Stop Conditions
SCL
SDA
START CONDITION
STOP CONDITION
3830 FHD F03
3830 FHD F04
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X24001
Programming Operation
Programming of the X24001 is performed one byte at a
time. After each byte is written, a delay equal to the write
cycle time of 5ms must be observed before initiating the
next write cycle.
The sequence of operations is: first raise the SCL pin to
VPGM and generate a HIGH to LOW transition of SDA
(programming mode start). This is followed by eight bits
of data containing the program command bits, four
address bits and two don’t care bits, immediately fol-
lowed by the 8-bit data byte.
The timing of the operation conforms to the standard
A.C. timing requirements and follows the sequence
shown below. After generating the Programming Mode
start condition the SCL HIGH level can be either VIH
or VPGM.
Figure 3. Programming Sequence
Factory Programming Service
The X24001 can be programmed with customer specific
data prior to shipment. The data programmed can be in
two forms: static data pattern where there is no change
in the data in a group of devices or sequential data, such
as a base number incremented by one for each device
tested and shipped.
Customers requiring one of these services should con-
tact their local sales office for ordering procedures and
service charges.
VPGM
SCL
VIH
SDA
S
T
A
R
T
0 1 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3830 FHD F05.1
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X24001
Read Operation
The byte read operation is initiated with a start condition.
The start condition is followed by an eight-bit control byte
which consists of a two-bit read command (1,0), four
address bits, and two “don’t care” bits. After receipt of
the control byte, the X24001 will enter the read mode
and transfer data into the shift register from the array.
This data is shifted out of the device on the next eight
SCL clocks. At the end of the read, all counters are reset
and the X24001 will enter the standby mode. As with a
write, the read operation can be interrupted by a start or
stop condition while the command or address is being
clocked in. While clocking data out, starts or stops
cannot be generated.
During the second don’t care clock cycle, starts and
stops are ignored. The master must free the bus prior to
the end of this clock cycle to allow the X24001 to begin
outputting data (Figures 4 and 5).
Figure 4. Read Sequence
START 1 0 A3 A2 A1 A0 XX XX D7 D6 D5 D4 D3 D2 D1 D0
3830 FHD F06
Figure 5. Read Cycle Timing
SCK
SDA IN
SDA OUT
6781
A0 XX XX
D7 D6
3830 FHD F07
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5