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Preliminary Information
XP2in4072N2o Connect
2K
X24022
Serial E2PROM
256 x 8 Bit
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 µA
Internally Organized 256 x 8
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
High Reliability
—Endurance: 100,000 Cycles Per Byte
—Data Retention: 100 Years
DESCRIPTION
The X24022 is a CMOS 2048 bit serial E2PROM, inter-
nally organized 256 x 8. The X24022 features a serial
interface and software protocol allowing operation on a
simple two wire bus. Three address inputs allow up to
eight devices to share a common two wire bus.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years. The X24022 is avail-
able in eight pin DIP and SOIC packages.
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
(5) SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(6) SCL
(3) A2
(2) A1
(1) A0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
PIN
XDEC
E2PROM
64 X 32
YDEC
8
CK DATA REGISTER DOUT
3848 FHD F01
© Xicor, 1991 Patents Pending
3848-1
1 Characteristics subject to change without notice

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X24022
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Guide-
lines for Calculating Typical Values of Bus Pull-Up
Resistors graph.
Address (A0, A1, A2)
The address inputs are used to set the least significant
three bits of the seven bit slave address. These inputs
can be static or actively driven. If used statically they
must be tied to VSS or VCC as appropriate. If actively
driven, they must be driven to VSS or to VCC.
PIN CONFIGURATION
A0
A1
A2
VSS
DIP/SOIC
18
27
X24022
36
45
VCC
NC
SCL
SDA
3848 FHD F02
PIN NAMES
Symbol
A0–A2
SDA
SCL
NC
VSS
VCC
Description
Address Inputs
Serial Data
Serial Clock
No Connect
Ground
+5V
3848 PGM T01
2

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X24022
DEVICE OPERATION
The X24022 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24022 will be considered a slave in all
applications.
Figure 1. Data Validity
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24022 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
SCL
SDA
DATA STABLE DATA
CHANGE
3848 FHD F06
3