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32K
X24321
4K x 8 Bit
400 KHz 2-Wire Serial E2PROM
FEATURES
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Operation
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Internally Organized 4K x 8 Bit
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Hardware Write Protect
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 1,000,000 Cycles
—Data Retention: 100 Years
8-Lead SOIC
DESCRIPTION
The X24321 is a CMOS Serial E2PROM Memory,
internally organized 4K x 8. The device features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24321. When the WP
pin is HIGH, the upper quadrant of the Serial E2PROM
array is protected against any nonvolatile write
attempts.
Xicor Serial E2PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
FUNCTIONAL DIAGRAM
SERIAL E2PROM DATA
AND ADDRESS (SDA)
SCL
COMMAND
DECODE
AND
CONTROL
LOGIC
S2
DEVICE
S1 SELECT
LOGIC
S0
PAGE
DECODE
LOGIC
WRITE
PROTECT
LOGIC
DATA REGISTER
Y DECODE LOGIC
E2PROM
ARRAY
4K x 8
WRITE VOLTAGE
WP CONTROL
7040 FM 01
©Xicor, 1995, 1996 Patents Pending
7040 3/27/97 T0/C0/D0 SH
Characteristics subject to change without notice
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X24321
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S0, S1, S2)
The device select inputs (S0, S1, S2) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to VSS or VCC as appro-
priate. If actively driven, they must be driven with
CMOS levels.
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled and the device can be written
normally. When this input is held HIGH, Write Protec-
tion is enabled, and nonvolatile writes are disabled to
the upper quadrant of the E2PROM array.
PIN NAMES
Symbol
S0, S1, S2
SDA
SCL
WP
VSS
VCC
PIN CONFIGURATION
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
7040 FRM T01
S0
S1
S2
VSS
8-LEAD SOIC
18
27
X24321
36
45
VCC
WP
SCL
SDA
7040 FM 02
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X24321
DEVICE OPERATION
The device supports a bidirectional, bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
7040 FM 03
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
7040 FM 04
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X24321
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a Write Operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
1
89
ACKNOWLEDGE
7040 FM 05
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X24321
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S0, S1, and S2. This allows up to 8
devices to share a single bus. These bits are
compared to the S0, S1, and S2 device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a Read Operation is selected. When it is zero
then a Write Operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E2PROM array is 128
pages by 32 bytes per page. The page address is
partially contained in the Address Byte 1 and partially in
bits 7 through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Refer to figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1 0 1 0 S 2 S1 S0 R/ W
SLAVE ADDRESS BYTE
HIGH ORDER ADDRESS
0 0 0 A0 A11 A10 A9 A8
ADDRESS BYTE 1
LOW ORDER ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
7040 FM 06
5