Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see Figure 4). For the X24C16 this is fixed as 1010[B].
Figure 4. Slave Address
1 0 1 0 A2 A1 A0 R/W
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The next three bits of the slave address field are the bank
select bits. They are used by the host to toggle between
the eight 256 x 8 banks of memory. These are, in effect,
the most significant bits for the word address.
The next three bits of the slave address are an extension
of the array’s address and are concatenated with the
Figure 5. Byte Write
eight bits of address in the word address field, providing
direct access to the whole 2048 x 8 array.
Following the start condition, the X24C16 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type). Upon a correct
compare the X24C16 outputs an acknowledge on the
SDA line. Depending on the state of the R/W bit, the
X24C16 will execute a read or write operation.
For a write operation, the X24C16 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
2048 words in the array. Upon receipt of the word address
the X24C16 responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C16
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C16
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
BUS ACTIVITY: A
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