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APPLICATION NOTES
AVA I L A B L E
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
X24C44• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
256 Bit
X24C44
Serial Nonvolatile Static RAM
16 x 16 Bit
FEATURES
Advanced CMOS Version of Xicor’s X2444
16 x 16 Organization
Single 5 Volt Supply
Ideal for use with Single Chip Microcomputers
—Static Timing
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
Software and Hardware Control of Nonvolatile
Functions
Auto Recall on Power-Up
TTL and CMOS Compatible
Low Power Dissipation
—Active Current: 10mA Maximum
—Standby Current: 50µA Maximum
8-Lead PDIP, Cerdip, and 8-Lead SOIC Packages
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
DESCRIPTION
The Xicor X24C44 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X24C44 is fabricated
with Xicor’s Advanced CMOS Floating Gate technology.
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
tion (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is com-
pleted in 2µs or less.
Xicor NOVRAMs are designed for unlimited write opera-
tions to RAM, either from the host or recalls from
E2PROM and a minimum 1,000,000 store operations.
Inherent data retention is specified to be greater than
100 years.
FUNCTIONAL DIAGRAM
NONVOLATILE
E2PROM
ROW
DECODE
STATIC
RAM
256-BIT
CONTROL
LOGIC
RECALL (6)
STORE (7)
CE (1)
DI (3)
SK (2)
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
COLUMN
DECODE
4-BIT
COUNTER
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3832-1.5 6/19/96 T2/C1/D1 NS
1
DO (4)
3832 FHD F01
Characteristics subject to change without notice

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X24C44
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. CE must remain HIGH following a
Read or Write command until the data transfer is com-
plete. CE LOW places the X24C44 in the low power
standby mode and resets the instruction register. There-
fore, CE must be brought LOW after the completion of an
operation in order to reset the instruction register in
preparation for the next command.
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
Data In is the serial data input.
Data Out (DO)
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
STORE
STORE LOW will initiate an internal transfer of data from
RAM to the E2PROM array.
RECALL
RECALL LOW will initiate an internal transfer of data
from E2PROM to the RAM array.
PIN CONFIGURATION
PDIP/CERDIP/SOIC
CE 1
8 VCC
SK 2
7 STORE
X24C44
DI 3
6 RECALL
DO 4
5 VSS
3832 FHD F02.2
PIN NAMES
Symbol
CE
SK
DI
DO
RECALL
STORE
VCC
VSS
Description
Chip Enable
Serial Clock
Serial Data In
Serial Data Out
Recall Input
Store Input
+5V
Ground
3832 PGM T01
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X24C44
DEVICE OPERATION
The X24C44 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C44
requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C44 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C44 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be stopped.
Restarting the clock will resume shifting of data.
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
WRDS and WREN
Internally the X24C44 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
operations to the E2PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO and STORE
Either the software STO instruction or a LOW on the
STORE input will initiate a transfer of data from RAM to
E2PROM. In order to safeguard against unwanted store
operations, the following conditions must be true:
• STO instruction issued or STORE input is LOW.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely (after the instruction but before 16 bits of data
are transferred), the instruction register will be reset and
the data that was shifted-in will be written to RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in will
be overwritten.
Table 1. Instruction Set
Instruction
WRDS (Figure 3)
STO (Figure 3)
Reserved
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Format, I2 I1 I0
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
X = Don't Care
A = Address
Operation
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E2PROM
N/A
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E2PROM Data into RAM
Read Data from RAM Address AAAA
3832 PGM T13
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X24C44
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
SLEEP
Because the X24C44 is a low power CMOS device, the
SLEEP instruction implemented on the first generation
NMOS device has been deleted. For systems convert-
ing from the X2444 to the X24C44 the software need not
be changed; the instruction will be ignored.
WRITE PROTECTION
The X24C44 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the “write enable” latch is in the reset
state, disabling any store operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C44 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C44 a
minimum of tPUR after VCC is stable.
Power-Down Data Protection
Because the X24C44 is a 5V only nonvolatile memory
device it may be susceptible to inadvertent stores to the
E2PROM array during power-down cycles. Power-up
cycles are not a problem because the “previous recall”
latch and “write enable” latch are reset, preventing any
possible corruption of E2PROM data.
Software Power-Down Protection
If the STORE and RECALL pins are tied to VCC through
a pull-up resistor and only software operations are
performed to initiate stores, there is little likelihood of an
inadvertent store. However, if these two lines are under
microprocessor control, positive action should be em-
ployed to negate the possibility of these control lines
bouncing and generating an unwanted store. The safest
method is to issue the WRDS command after a write
sequence and also following store operations. Note: an
internal store may take up to 5ms; therefore, the host
microprocessor should delay 5ms after initiating the
store prior to issuing the WRDS command.
Hardware Power-Down Protection
(when the “write enable” latch and “previous recall” latch
are not in the reset state):
Holding either RECALL LOW, CE LOW or STORE
HIGH during power-down will prevent an inadvertent
store.
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X24C44
Figure 1. RAM Read
CE
SK 1 2 3 4 5 6 7 8 9 10 11 12 22 23 24
DI 1 A A A A 1 1 X*
HIGH Z
DO
*Bit 8 of Read Instructions is Don’t Care
Figure 2. RAM Write
CE
D0 D1 D2 D3 D13 D14 D15 D0
3832 FHD F07.1
SK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24
DI 1 A A A A 0 1 1 D0 D1 D2 D12 D13 D14 D15
3832 FHD F08.1
Figure 3. Non-Data Operations
CE
SK 1 2 3 4 5 6 7 8
DI 1 X X X X I2 I1 I0
3832 FHD F09.1
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