The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
Because the X24C44 is a low power CMOS device, the
SLEEP instruction implemented on the first generation
NMOS device has been deleted. For systems convert-
ing from the X2444 to the X24C44 the software need not
be changed; the instruction will be ignored.
The X24C44 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
Upon power-up the “write enable” latch is in the reset
state, disabling any store operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
The X24C44 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C44 a
minimum of tPUR after VCC is stable.
Power-Down Data Protection
Because the X24C44 is a 5V only nonvolatile memory
device it may be susceptible to inadvertent stores to the
E2PROM array during power-down cycles. Power-up
cycles are not a problem because the “previous recall”
latch and “write enable” latch are reset, preventing any
possible corruption of E2PROM data.
Software Power-Down Protection
If the STORE and RECALL pins are tied to VCC through
a pull-up resistor and only software operations are
performed to initiate stores, there is little likelihood of an
inadvertent store. However, if these two lines are under
microprocessor control, positive action should be em-
ployed to negate the possibility of these control lines
bouncing and generating an unwanted store. The safest
method is to issue the WRDS command after a write
sequence and also following store operations. Note: an
internal store may take up to 5ms; therefore, the host
microprocessor should delay 5ms after initiating the
store prior to issuing the WRDS command.
Hardware Power-Down Protection
(when the “write enable” latch and “previous recall” latch
are not in the reset state):
Holding either RECALL LOW, CE LOW or STORE
HIGH during power-down will prevent an inadvertent