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APPLICATION NOTE
A V A I LABLE
AN84
128K
X24F128
16K x 8 Bit
2-Wire SerialFlash with Block LockTM Protection
FEATURES
Save Critical Data With Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E2PROM Array)
—Software Program Protection
—Programmable Hardware Program Protect
In Circuit Programmable ROM Mode
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1µA
1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
32 Word Sector Program Mode
—Minimizes Total Program Time Per Word
100KHz 2-Wire Serial Interface
Internally Organized 16K x 8
Bidirectional Data Transfer Protocol
Self-Timed Program Cycle
—Typical Program Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8-Lead DIP
16-Lead SOIC
DESCRIPTION
The X24F128 is a CMOS SerialFlash Memory, inter-
nally organized 16K x 8. The device features a serial
interface and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
A Program Protect Register at the address location
FFFFh provides three program protection features:
Software Program Protect, Block Lock Protect, and
Hardware Program Protect. The Software Program
Protect feature prevents any nonvolatile writes to the
device until the PEL bit in the Program Protect
Register is set. The Block Lock Protection feature
allows the user to individually block protect four blocks
of the array by programming two bits in the Program
Protect Register. The Programmable Hardware
Program Protect feature allows the user to install the
device with PP tied to VCC, program the entire memory
array in circuit, and then enable the hardware program
protection by programming a PPEN bit in the Program
Protect Register. After this, selected blocks of the
array, including the Program Protect Register itself, are
permanently protected from being erased.
FUNCTIONAL DIAGRAM
SERIALFLASH DATA
AND ADDRESS (SDA)
SCL
COMMAND
DECODE
AND
CONTROL
LOGIC
SECTOR
DECODE
LOGIC
BLOCK LOCK AND
PROGRAM PROTECT
CONTROL LOGIC
S2
DEVICE
S1 SELECT
LOGIC
S0
PROGRAM
PROTECT
REGISTER
DATA REGISTER
Y DECODE LOGIC
SERIALFLASH
ARRAY
16K x 8
4K x 8
4K x 8
8K x 8
PP
©Xicor, 1995, 1996 Patents Pending
7012-0.8 11/25/96 T1/C0/D0 SH
PROGRAM VOLTAGE
CONTROL
7012 ILL F01.4
Characteristics subject to change without notice
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X24F128
Xicor SerialFlash Memories are designed and tested
for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S0, S1, S2)
The device select inputs (S0, S1, S2) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to VSS or VCC as appro-
priate. If actively driven, they must be driven with
CMOS levels.
Program Protect (PP)
The Program Protect input controls the Hardware
Program Protect feature. When held LOW, hardware
program protection is disabled and the device can be
programmed normally. When this input is held HIGH,
and the PPEN bit in the Program Protect Register is
set HIGH, program protection is enabled, and nonvola-
tile writes are disabled to the selected blocks as well
as the Program Protect Register itself.
PIN NAMES
Symbol
S0, S1, S2
SDA
SCL
PP
VSS
VCC
NC
PIN CONFIGURATION
Description
Device Select Inputs
Serial Data
Serial Clock
Program Protect
Ground
Supply Voltage
No Connect
7012 FRM T01
S0
S1
S2
VSS
8-LEAD DIP
18
27
X24F128
36
45
VCC
PP
SCL
SDA
S0
S1
NC
NC
NC
NC
S2
VSS
16-LEAD SOIC
1 16
2 15
3 14
4 13
X24F128
5 12
6 11
7 10
89
VCC
PP
NC
NC
NC
NC
SCL
SDA
7012 ILL F02.1
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X24F128
DEVICE OPERATION
The device supports a bidirectional, bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the X24F128 will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
7012 ILL F03
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
7012 ILL F04
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X24F128
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a program operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
89
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7012 ILL F05
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X24F128
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S0, S1, and S2. This allows up to 8
devices to share a single bus. These bits are
compared to the S0, S1, and S2 device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a program operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E2 array is 512 sectors
by 32 bytes per sector. The sector address is partially
contained in the Address Byte 1 and partially in bits 7
through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Refer to figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1 0 1 0 S2 S1 S0 R/W
SLAVE ADDRESS BYTE
HIGH ORDER ADDRESS
0 0 A13 A12 A11 A10 A9 A8
ADDRESS BYTE 1
LOW ORDER ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
7012 ILL F06.1
5