The X25401 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the
entire data transfer operation.
Table 1 contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X25401
requires the instruction to be shifted in with the MSB
After CS is LOW, the X25401 will not begin to interpret
the data stream until a logic “1” has been shifted in on
SI. Therefore, CS may be brought LOW with SCK
running and SI LOW. SI must then go HIGH to indicate
the start condition of an instruction before the X25401
will begin any action.
In addition, the SCK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is
reset upon power-up and must be intentionally set by
the user to enable any write or store operations. Al-
though a recall operation is performed upon power-up,
the previous recall latch is not set by this operation.
WRDS and WREN
Internally the X25401 contains a “write enable” latch.
This latch must be set for either writes to the RAM or
store operations to the E2PROM. The WREN instruction
sets the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
The software STO instruction will initiate a transfer of
data from RAM to E2PROM. In order to safeguard
against unwanted store operations, the following con-
ditions must be true:
• STO instruction issued.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
TABLE 1. INSTRUCTION SET
WRDS (Figure 3)
STO (Figure 3)
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Format, I2 I1 I0
X = Don’t Care
A = Address
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E2PROM
Enable AUTOSTORE Feature
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E2PROM Data into RAM
Read Data from RAM Address AAAA
2051 PGM T11