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APPLICATION NOTE
AVA I L A B L E
X25401
AN56
256 Bit
X25401
SPI Serial AUTOSTORE™ NOVRAM
16 x 16 Bit
FEATURES
1MHz Clock Rate
AUTOSTORE™ NOVRAM
—Automatically Performs a Store Operation
Upon Loss of VCC
Single 5 Volt Supply
Ideal for use with Single Chip Microcomputers
—Minimum I/O Interface
—SPI Mode (0,0 & 1,1) Serial Port Compatible
—Easily Interfaced to Microcontroller Ports
Software and Hardware Control of Nonvolatile
Functions
Auto Recall on Power-Up
TTL and CMOS Compatible
Low Power Dissipation
—Active Current: 10mA
—Standby Current: 50µA
8-Lead PDIP and 8-Lead SOIC Packages
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
DESCRIPTION
The Xicor X25401 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X25401 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
tion (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is com-
pleted in 2µs or less.
The X25401 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when VCC falls below a preset threshold.
Xicor NOVRAMs are designed for unlimited write opera-
tions to RAM, either from the host or recalls from E2PROM
and a minimum 1,000,000 store operations. Inherent data
retention is specified to be greater than 100 years.
NONVOLATILE
E2PROM
ROW
DECODE
STATIC
RAM
256-BIT
CONTROL
LOGIC
RECALL (6)
AS (7)
CS (1)
SI (3)
SCK (2)
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
COLUMN
DECODE
4-BIT
COUNTER
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1992, 1995, 1996 Patents Pending
2051-1.5 8/1/97 T0/C0/D2 SH
1
SO (4)
2051 FHD F01
Characteristics subject to change without notice

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X25401
PIN DESCRIPTIONS
Chip Select (CS)
The Chip Select input must be LOW to enable all read/
write operations. CS must remain LOW following a
Read or Write command until the data transfer is com-
plete. CS HIGH places the X25401 in the low power
standby mode and resets the instruction register. There-
fore, CS must be brought HIGH after the completion of
an operation in order to reset the instruction register in
preparation for the next command.
Serial Clock (SCK)
The Serial Clock input is used to clock all data into and
out of the device.
Serial Data In (SI)
SI is the serial data input.
Serial Data Out (SO)
SO is the serial data output. It is in the high impedance
state except during data output cycles in response to a
READ instruction.
AUTOSTORE Output (AS)
AS is an open drain output which, when asserted indi-
cates VCC has fallen below the AUTOSTORE thresh-
old (VASTH). AS may be wire-ORed with multiple open
drain outputs and used as an interrupt input to a micro-
controller or as an input to a low power reset circuit.
RECALL
RECALL LOW will initiate an internal transfer of data
from E2PROM to the RAM array.
PIN CONFIGURATION
CS
SCK
SI
SO
DIP/SOIC
18
27
X25401
36
45
VCC
AS
RECALL
VSS
2051 FHD F02
PIN NAMES
Symbol
CS
SCK
SI
SO
RECALL
AS
VCC
VSS
Description
Chip Enable
Serial Clock
Serial Data In
Serial Data Out
Recall Input
AUTOSTORE Output
+5V
Ground
2051 PGM T01
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X25401
DEVICE OPERATION
The X25401 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the
entire data transfer operation.
Table 1 contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X25401
requires the instruction to be shifted in with the MSB
first.
After CS is LOW, the X25401 will not begin to interpret
the data stream until a logic “1” has been shifted in on
SI. Therefore, CS may be brought LOW with SCK
running and SI LOW. SI must then go HIGH to indicate
the start condition of an instruction before the X25401
will begin any action.
In addition, the SCK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
RCL and RECALL
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is
reset upon power-up and must be intentionally set by
the user to enable any write or store operations. Al-
though a recall operation is performed upon power-up,
the previous recall latch is not set by this operation.
WRDS and WREN
Internally the X25401 contains a “write enable” latch.
This latch must be set for either writes to the RAM or
store operations to the E2PROM. The WREN instruction
sets the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to E2PROM. In order to safeguard
against unwanted store operations, the following con-
ditions must be true:
• STO instruction issued.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
TABLE 1. INSTRUCTION SET
Instruction
WRDS (Figure 3)
STO (Figure 3)
ENAS
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Format, I2 I1 I0
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
X = Don’t Care
A = Address
Operation
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E2PROM
Enable AUTOSTORE Feature
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E2PROM Data into RAM
Read Data from RAM Address AAAA
2051 PGM T11
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X25401
WRITE
The WRITE instruction contains the 4-bit address of
the word to be written. The write instruction is immedi-
ately followed by the 16-bit word to be written. CS must
remain LOW during the entire operation. CS must go
HIGH before the next rising edge of SCK. If CS is
brought HIGH prematurely (after the instruction but
before 16 bits of data are transferred), the instruction
register will be reset and the data that was shifted-in
will be written to RAM.
If CS is kept LOW for more than 24 SCK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
I0 of the instruction word is a “don’t care”. This provides
two advantages. In a design that ties both SI and SO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an
output to an input. Secondly, it allows for valid data
output during the ninth SCK clock cycle.
All data bits are clocked by the falling edge of SCK
(refer to Read Cycle Diagram).
LOW POWER MODE
When CS is HIGH, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X25401 to
automatically perform a store operation when VCC falls
below the AUTOSTORE threshold (VASTH).
WRITE PROTECTION
The X25401 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any
store operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hard-
ware recall operation, which assures that data in all
RAM locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X25401 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X25401
a minimum of tPUR after VCC is stable.
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X25401
Figure 1. RAM Read
CS
SCK
1 2 3 4 5 6 7 8 9 10 11 12 22 23 24
SI 1 A A A A 1 1 X*
HIGH Z
SO
*Bit 8 of Read Instructions is Don’t Care
Figure 2. RAM Write
CS
D0 D1 D2 D3 D13 D14 D15 D0
2051 FHD F09.1
SK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24
DI 1 A A A A 0 1 1 D0 D1 D2 D12 D13 D14 D15
Figure 3. Non-Data Operations
2051 FHD F10.1
CS
SCK
12345678
SI 1 X X X X I2 I1 I0
2051 FHD F11.1
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