Clock and Data Timing
Data input on the SI line is sampled and latched on the
rising edge of SCK. Data is output on the SO line by the
falling edge of SCK.
The CS line is first pulled LOW to select the device. The
8-bit read opcode is transmitted to the X25C02, fol-
lowed by the 8-bit address. After the READ opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
read sequentially by continuing to provide clock pulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($FF) the
address counter rolls over to address $00 allowing the
read cycle to be continued indefinitely. The read opera-
tion is terminated by taking CS HIGH. Refer to the read
operation sequence illustrated in Figure 1.
Prior to any attempt to write data into the X25C02, the
“write enable” latch must first be set by issuing the
WREN instruction (See Fig. 2). CS is first taken LOW,
then the instruction is clocked into the X25C02. After all
eight bits of the instruction are transmitted, CS must then
be taken HIGH. If the user continues the write operation
without taking CS HIGH after issuing the WREN instruc-
tion, the write operation will be ignored.
Once the “write enable” latch is set, the user may
proceed by issuing the write instruction, followed by the
address and then the data to be written. This is minimally
a twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25C02. The only restriction is the four bytes must
reside on the same page. A page address begins with
address XXXX XX00 and ends with XXXX XX11. If the
byte address counter reaches XXXX XX11 and the clock
continues the counter will “roll over” to the first address
of the page and overwrite any data that may have been
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after the
twenty-fourth, thirty-second, fourtieth or fourty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 for a
detailed illustration of the page write sequence and time
frames in which CS going HIGH are valid.
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when HOLD is first pulled low and SCK must also
be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.