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APPLICATION NOTES
AVA I L A B L E
X25C02AN9 • AN18 • AN31 • AN37 • AN40
2K
X25C02
SPI Serial E2PROM
256 x 8 Bit
FEATURES
1MHz Clock Rate
256 X 8 Bits
—4 Byte Page Mode
Low Power CMOS
—150µA Standby Current
—2mA Active Current
5V Power Supply
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Available Packages
—8-Lead MSOP
—8-Lead PDlP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E2PROM, inter-
nally organized as 256 x 8. The X25C02 features a serial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25C02 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
The X25C02 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Writeis a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3843-1.6 6/10/96 T5/C1/D1 NS
X 64
DECODE
LOGIC
256 BYTE ARRAY
(64 X 32)
48
Y DECODE
DATA REGISTER
3843 FHD F01
Characteristics subject to change without notice
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X25C02
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All data, opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are sampled or latched on the rising edge
of the clock input, while data on the SO pin change after
the falling edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25C02 is deselected and the
SO output pin is at HIGH impedance and unless an
internal write operation is underway, the X25C02 will be
PIN CONFIGURATION
CS
SO
WP
VSS
MSOP/DIP/SOIC
18
27
X25C02
36
45
VCC
HOLD
SCK
SI
3843 FHD F02.2
in the standby power mode. CS LOW enables the
X25C02, placing it in the active power mode. It should be
noted that after power-up, a HIGH to LOW transition on
CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25C02 are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25C02. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
3843 PGM T01
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X25C02
PRINCIPLES OF OPERATION
The X25C02 is a 256 x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25C02 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and WP
inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25C02 into
a “PAUSE” condition. After releasing HOLD, the X25C02
will resume operation from the point when HOLD was
first asserted.
Write Enable (WREN) and Write Disable (WRDI)
The X25C02 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte or page write cycle. The latch is
also reset if WP is brought LOW.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
READ
0000 0011
Read Data from Memory Array beginning at selected ad-
dress
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3843 PGM T02
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X25C02
DEVICE OPERATION
Clock and Data Timing
Data input on the SI line is sampled and latched on the
rising edge of SCK. Data is output on the SO line by the
falling edge of SCK.
Read Sequence
The CS line is first pulled LOW to select the device. The
8-bit read opcode is transmitted to the X25C02, fol-
lowed by the 8-bit address. After the READ opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
read sequentially by continuing to provide clock pulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($FF) the
address counter rolls over to address $00 allowing the
read cycle to be continued indefinitely. The read opera-
tion is terminated by taking CS HIGH. Refer to the read
operation sequence illustrated in Figure 1.
Write Sequence
Prior to any attempt to write data into the X25C02, the
“write enable” latch must first be set by issuing the
WREN instruction (See Fig. 2). CS is first taken LOW,
then the instruction is clocked into the X25C02. After all
eight bits of the instruction are transmitted, CS must then
be taken HIGH. If the user continues the write operation
without taking CS HIGH after issuing the WREN instruc-
tion, the write operation will be ignored.
Once the “write enable” latch is set, the user may
proceed by issuing the write instruction, followed by the
address and then the data to be written. This is minimally
a twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25C02. The only restriction is the four bytes must
reside on the same page. A page address begins with
address XXXX XX00 and ends with XXXX XX11. If the
byte address counter reaches XXXX XX11 and the clock
continues the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after the
twenty-fourth, thirty-second, fourtieth or fourty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 for a
detailed illustration of the page write sequence and time
frames in which CS going HIGH are valid.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when HOLD is first pulled low and SCK must also
be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
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X25C02
Operational Notes
The X25C02 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Figure 1. Read Operation Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
The “write enable” latch is reset when WP is brought LOW.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
SI
BYTE ADDRESS
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
3843 FHD F04.1
Figure 2. Set Write Enable Latch Sequence
CS
SCK
01234567
SI
HIGH IMPEDANCE
SO
3843 FHD F05.1
5