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4K
X25F047
512 x 8 Bit
SPI SerialFlash with Block LockTM Protection
FEATURES
• 1MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 512 x 8 Bits
—16 Byte Small Sector Program Mode
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Program
—<400µA Active Current during Read
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• Block Lock Protection
—Block Lock Protect 0, any 1/4, 1st 1/2, First or
Last Sector of SerialFlash Array
• Built-in Inadvertent Program Protection
—Power-Up/Power-Down Protection Circuitry
—Program Enable Latch
—Program Protect Pin
• Self-Timed Program Cycle
—5ms Program Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead SOIC Package
• 8-Lead MSOP Package
• 8-Lead TSSOP Package
• 8-Pin Mini-DIP Package
FUNCTIONAL DIAGRAM
DESCRIPTION
The X25F047 is a CMOS 4K-bit SerialFlash, internally
organized as 512 x 8. The X25F047 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are eight options for programmable, nonvolatile,
Block Lock Protection available to the end user. These
options are implemented via special instructions
programmed to the part. The X25F047 also features a
PP pin that can be used for hardwire protection of the
part, disabling all programming attempts, as well as a
Program Enable Latch that must be set before a program
operation can be initiated.
The X25F047 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
SI
SO
SCK
CS
COMMAND
DECODE
AND
CONTROL
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
X
DECODE
LOGIC
32
SERIALFLASH
ARRAY
(512 x 8)
PP PROGRAM CONTROL LOGIC
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7005-0.9 5/7/97 T4/C0/D1
1
HIGH VOLTAGE
CONTROL
7005 FRM 01.3
Characteristics subject to change without notice

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X25F047
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be programmed to the memory are input on
this pin. Data is latched by the rising edge of the serial
clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25F047 is deselected and the
SO output pin is at high impedance and unless a nonvol-
atile write cycle is underway, the X25F047 will be in the
standby power mode. CS LOW enables the X25F047,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Program Protect (PP)
When PP is LOW, nonvolatile writes to the X25F047 are
disabled, but the part otherwise functions normally. When
PP is held HIGH, all functions, including nonvolatile
writes, operate normally. PP going LOW while CS is still
LOW will interrupt a programming cycle to the X25F047.
If the nonvolatile write cycle has already been initiated,
PP going low will have no affect on this cycle.
PIN NAMES
Symbol
CS
SO
SI
SCK
PP
VSS
VCC
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Program Protect Input
Ground
Supply Voltage
No Connect
7005 FRM T01
PIN CONFIGURATION
8-LEAD SOIC/DIP
Not to scale
*0.197"
CS
SO
PP
V SS
18
27
X25F047
36
45
V CC
NC
SCK
SI
0.120"
SO
CS
VSS
PP
*0.244"
8-LEAD MSOP
18
27
X25F047
36
45
V CC
NC
SI
SCK
0.122"
NC
VCC
CS
SO
0.193"
8-LEAD TSSOP
1
2
X25F047
3
4
8
7
6
5
SCK
SI
V SS
PP
*SOIC Measurement
0.252"
7005 FRM 02
PRINCIPLES OF OPERATION
The X25F047 is a 512 x 8 SerialFlash designed to inter-
face directly with the synchronous Serial Peripheral Inter-
face (SPI) of many popular microcontroller families.
The X25F047 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW and the PP
input must be HIGH during the entire operation. Table 1
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera-
tions where left off.
Program Enable Latch
The X25F047 contains a “Program Enable” latch. This
latch must be SET before a program operation is initi-
ated. The PREN instruction will set the latch and the
PRDI instruction will reset the latch (Figure 4). This latch
is automatically reset upon a power-up condition and
after the completion of a sector program cycle.
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X25F047
Block Lock Protection
There are eight Block Lock Protection options. The pre-
defined blocks and associated address ranges are pro-
tected by programming the appropriate two byte
Program Status instruction to the device (Table 1 and
Figure 6). Once a Block Lock protect instruction has
been completed, that Block Lock Protection setup is held
in a nonvolatile Status Register (Figure 1) until the next
Program Status instruction is issued. The sections of the
memory array that are Block Lock protected can be read
but not programmed until Block Lock Protection is
removed or changed.
Figure 1. Status Register/Block Lock Protection Byte
76543210
0 0 0 0 0 BL2 BL1 BL0
Note: Bits [7:3] specified to be “0’s”
7005 FRM T02.1
Read Sequence
When reading from the SerialFlash memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25F047, followed by the
16-bit address, of which the last 9 bits are used (bits
[15:9] specified to be "0’s"). After the READ opcode and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO line. The data
stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached (01FFh), the address counter
rolls over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by taking CS HIGH (Figure 2).
Sector Program Sequence
Prior to any attempt to program data into the X25F047,
the “Program Enable” latch must first be set by issuing
the PREN instruction (Table 1 and Figure 4). CS is first
taken LOW. Then the PREN instruction is clocked into
the X25F047. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the program operation without taking CS HIGH
after issuing the PREN instruction, the program opera-
tion will be ignored.
To program data to the SerialFlash memory array, the
user then issues the PROGRAM instruction, followed by
the 16 bit address of the first location in the sector and
then the 16 bytes of data to be programmed. Only the last
9 bits of the address are used and bits [15:9] are speci-
fied to be "0’s". The entire write operation takes 152
clocks. CS must go LOW and remain LOW for the dura-
tion of the operation. The host must program 16 bytes in
each write with the restriction that these bytes reside on
one sector. If the address counter reaches the end of the
sector and the clock continues, or if fewer than 16 bytes
are clocked in, the contents of the sector cannot be guar-
anteed.
For a sector program operation to be completed, CS can
only be brought HIGH after bit 0 of the last data byte to
be programmed is clocked in. If it is brought HIGH at any
other time, the program operation will not be completed.
(Figure 5)
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the Block Lock Protection byte
from the Status Register which contains the Block Lock
Protection bits BL2-BL0 (Figure 1). The Block Lock Pro-
tection bits define the Block Lock Protection condition
(Figure 1 and Table1). The other bits are reserved and
will return "0’s" when read (Figure 3).
If a nonvolatile write is in progress, the Read Status
instruction returns the status of the internal write opera-
tion on SO. When the nonvolatile write cycle is com-
pleted, the status register data is again read out.
During a nonvolatile write in progress, the SO pin will be
set HIGH. At the end of the nonvolatile write cycle, SO is
set to output the current bit from the status register.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (Figure 3). When the pointer reaches the
end of the eight bit status register, it “rolls over” to the first
bit of the register.
Program Status Operation
Prior to any attempt to perform a Program Status Opera-
tion, the PREN instruction must first be issued. This
instruction sets the “Program Enable” latch and allows
the part to respond to a Program Status sequence (Fig-
ure 6). The Program Status instruction follows and con-
sists of one command byte followed by one Block Lock
Protection byte (Figure 1). This byte contains the Block
Lock Protection bits BL2-BL0. The rest of the bits [7:3]
are unused and must be programmed as “0’s”. Bringing
CS HIGH after the two byte Program Status instruction
initiates a nonvolatile write to the Status Register. Pro-
gramming more than one byte to the Status Register will
overwrite the previously programmed Block Lock Protec-
tion byte (Table 1).
3

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X25F047
Data Protection
The following circuitry has been included to prevent inad-
vertant programming of data:
• The “Program Enable” latch is reset upon power-up.
• A PREN instruction must be issued to set the “Program
Enable” latch.
• CS must come HIGH at the proper clock count in order
to start a program cycle.
Operational Notes
The X25F047 powers up in the following state:
• The device is in the low power, standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is at high impedance.
• The “Program Enable” latch is reset.
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction
Format*
Instruction Name and Operation
0000 0110
PREN: Set the Program Enable Latch (Program Enable Operation)
0000 0100
PRDI: Reset the Program Enable Latch (Program Disable Operation)
0000 0001
PROGRAM STATUS Instruction - followed by:
Block Lock Protection Byte: (Figure 1)
0000 0000 --->NO PROTECT: ---------------------------------->None of the Array
0000 0001 --->PROTECT Q1: --- 0000h - 007Fh ---------->Lower Quadrant (Q1)
0000 0010 --->PROTECT Q2: --- 0080h - 00FFh----------->Q2
0000 0011 --->PROTECT Q3: --- 0100h - 017Fh----------->Q3
0000 0100 --->PROTECT Q4: --- 0180h - 01FFh----------->Upper Quadrant (Q4)
0000 0101 --->PROTECT H1: --- 0000h - 00FFh----------->Lower Half of the Array (H1)
0000 0110 --->PROTECT S0: --- 0000h - 000Fh----------->Lower Sector (S0)
0000 0111 --->PROTECT Sn: --- 01F0h - 01FFh----------->Upper Sector (Sn)
0000 0101
READ STATUS: Reads Block Lock Protection & nonvolatile write in progress status on SO Pin
0000 0010
PROGRAM: Program operation followed by address and data
0000 0011
READ: Read operation followed by address
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
7005 FRM T03.1
Figure 2. Read Operation Sequence
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30
READ INSTRUCTION
(1 BYTE)
BYTE ADDRESS (2 BYTE)
15 14
3210
DATA OUT
HIGH IMPEDANCE
SO
76543210
7005 FRM F03.1
4

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X25F047
Figure 3. Read Status Operation Sequence
CS
SCK
SI
SO
01234567
READ STATUS
INSTRUCTION
NONVOLATILE WRITE IN PROGRESS
SO HIGH DURING
NONVOLATILE
WRITE CYCLE
Figure 4. Program Enable/Program Disable Sequence
CS
SCK
SI
01234567
INSTRUCTION
(1 BYTE)
HIGH IMPEDANCE
SO
...
...
...B B B
LL L
21 0
SO = STATUS REG BIT
WHEN NO NONVOLATILE
WRITE CYCLE
7005 FRM 04.2
7005 FRM 05.1
5