Read operations are initiated by both OE and CE LOW
and WE HIGH. The read operation is terminated by
either CE or OE returning HIGH. This two line control
architecture eliminates bus contention in a system envi-
ronment. The data bus will be in a high impedance state
when either OE or CE is HIGH.
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X2804C supports both a CE
and WE controlled write cycle. That is, the address is
latched by the falling edge of either CE or WE, whichever
occurs last. Similarly, the data is latched internally by the
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X2804C allows the entire
memory to be typically written in 450ms. Page write
allows two to sixteen bytes of data to be consecutively
written to the X2804C prior to the commencement of the
internal programming cycle. Although the host system
may read data from any other device in the system to
transfer to the X2804C, the destination page address of
the X2804C should be the same on each subsequent
strobe of the WE and CE inputs. That is, A4 through A10
must be the same for each transfer of data to the
X2804C during a page write cycle.
The page write mode can be entered during any write
operation. Following the initial byte write cycle, the host
can write an additional one to fifteen bytes in the same
manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW
transition, must begin within 20µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 20µs, the internal auto-
matic programming cycle will commence. There is no
page write window limitation. The page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 20µs.
The X2804C features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X2804C,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
There are three features that protect the nonvolatile data
from inadvertent writes.
• Noise Protection—A WE pulse which is typically
less than 10ns will not initiate a write cycle.
• VCC Sense—All functions are inhibited when VCC is
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH during power-up and power-down, will
inhibit inadvertent writes. Write cycle timing specifi-
cations must be observed concurrently.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance.