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X28HT010
1M
X28HT010
128K x 8 Bit
High Temperature, 5 Volt, Byte Alterable E2PROM
FEATURES
175°C Full Functionality
Simple Byte and Page Write
—Single 5V Supply
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Highly Reliable Direct Write™ Cell
—Endurance: 10,000 Write Cycles
—Data Retention: 100 Years
—Higher Temperature Functionality is Possible
by Operating in the Byte Mode.
DESCRIPTION
The Xicor X28HT010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology which provides Xicor products supe-
rior high temperature performance characteristics. Like
all Xicor programmable non-volatile memories the
X28HT010 is a 5V only device. The X28HT010 features
the JEDEC approved pinout for byte-wide memories,
compatible with industry standard EPROMs.
The X28HT010 supports a 256-byte page write opera-
tion, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
PIN CONFIGURATIONS
VBB
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
FLAT PACK
CERDIP
SOIC (R)
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
X28HT010
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
6613 FHD F02
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
6613-1.5 8/5/97 T2/C0/D0 EW
1
PGA
I/O0 I/O2 I/O3 I/O5 I/O6
15 17 19 21 22
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
A2 A3
12 11
A10 OE
25 26
A4 A5
X28HT010
A11 A9
10 9
27 28
(BOTTOM VIEW)
A6 A7
87
A8 A13
29 30
A12 A15 NC VCC NC NC A14
6 5 2 36 34 32 31
A16 VBB NC WE NC
4 3 1 35 33
6613 FHD F21
Characteristics subject to change without notice

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X28HT010
PIN DESCRIPTIONS
Addresses (A0–A16)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HT010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HT010.
Back Bias Voltage (VBB)
It is required to provide -3V on pin 1. This negative
voltage improves higher temperature functionality.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol
A0–A16
I/O0–I/O7
WE
CE
OE
VBB
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
–3V
+5V
Ground
No Connect
6613 PGM T01
A8–A16
X BUFFERS
LATCHES AND
DECODER
1M-BIT
E2PROM
ARRAY
A0–A7
Y BUFFERS
LATCHES AND
DECODER
CE
OE
WE
VCC
VSS
VBB
CONTROL
LOGIC AND
TIMING
2
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
6613 FHD F01

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X28HT010
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HT010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28HT010 allows the
entire memory to be written in 5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28HT010 prior to the
commencement of the internal programming cycle. The
host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A8 through A16) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty-six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
HARDWARE DATA PROTECTION
The X28HT010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
Default VCC Sense—All functions are inhibited when
VCC is 3.4V.
Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SYSTEM CONSIDERATIONS
Because the X28HT010 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation
and eliminate the possibility of contention where mul-
tiple I/O pins share the same bus.
It has been demonstrated that markedly higher tem-
perature performance can be obtained from this device
if CE is left enabled throughout the read and write
operation.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HT010 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
3

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X28HT010
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28HT010 ................................. –55°C to +175°C
Voltage on any Pin with
Respect to VSS ....................................... –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMEND OPERATING CONDITIONS
Temperature
Min.
Max.
High Temp.
–40°C
+175°C
6613 PGM T02.2
Supply Voltages
X28HT010
Back Bias Voltage: v
Limits
5V ±5%
–3V ±10%
6613 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Symbol
ICC
Parameter
VCC Current (Active)
(TTL Inputs)
Limits
Min.
Max.
50
ISB1
ILI
ILO
VlL(1)
VIH(1)
VOL
VOH
IBB
VCC Current (Standby)
(TTL Inputs)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Back Bias Current
3
20
20
–1 0.6
2.2 VCC + 1
0.5
2.6
200
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
Units
mA
mA
µA
µA
V
V
V
V
µA
Test Conditions
CE = OE = VIL, WE = VIH,
All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 5MHz
CE = VIH, OE = VIL
All I/O’s = Open, Other Inputs = VIH
VIN = VSS to VCC
VOUT = VSS to VCC, CE = VIH
IOL = 1mA
IOH = –400µA
VBB = –3V ±10%
6613 PGM T04.2
4

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X28HT010
POWER-UP TIMING
Symbol
tPUR(2)
tPUW(2)
Parameter
Power-up to Read Operation
Power-up to Write Operation
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
CI/O(2)
CIN(2)
Input/Output Capacitance
Input Capacitance
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Data Retention
Min.
10,000
100
Max.
100
5
Max.
10
10
Units
pF
pF
Max.
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
Input and Output
Timing Levels
10ns
1.5V
6613 PGM T08.1
MODE SELECTION
CE OE WE
L LH
LHL
HXX
XLX
XXH
Mode
Read
Write
Standby and
Write Inhibit
Write Inhibit
Write Inhibit
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
Units
µs
ms
6613 PGM T05
Test Conditions
VI/O = 0V
VIN = 0V
6613 PGM T06.1
Units
Cycles per Byte
Years
6613 PGM T07
I/O
DOUT
DIN
High Z
Power
Active
Active
Standby
——
——
6613 PGM T09
5V
WAVEFORM INPUTS
OUTPUTS
1.92K
OUTPUT
1.37K
100pF
6613 FHD F04.3
Note: (2) This parameter is periodically sampled and not 100%
tested.
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5