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X28LC512/X28LC513
512K
X28LC512/X28LC513
3.3 Volt, Byte Alterable E2PROM
64K x 8 Bit
FEATURES
Low VCC Operation: VCC = 3.3V ±10%
Access Time: 150ns
Simple Byte and Page Write
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 25mA
—Standby: 150µA
Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
High Speed Page Write Capability
Highly Reliable Direct Write™ Cell
—Endurance: 10,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
DATA Polling
—Toggle Bit Polling
PIN CONFIGURATIONS
Two PLCC and LCC Pinouts
—X28LC512
—X28LC010 E2PROM Pin Compatible
—X28LC513
—Compatible with Lower Density E2PROMs
DESCRIPTION
The X28LC512/513 is a low-power 64K x 8 E2PROM,
fabricated with Xicor’s proprietary, high performance,
floating gate CMOS technology. The X28LC512/513
features the JEDEC approved pinout for bytewide memo-
ries, compatible with industry standard EPROMS.
The X28LC512/513 supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less than
2.5 seconds. The X28LC512/513 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28LC512/513 supports the Soft-
ware Data Protection option.
PLCC
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
PLASTIC DIP
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
X28LC512
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3005 ILL F02.1
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3005-3.2 8/5/97 T2/C0/D0 EW
TSOP
X28LC512
1
40 OE
39 A10
38 CE
37 I/O7
36 I/O6
35 I/O5
34 I/O4
33 I/O3
32 NC
31 NC
30 VSS
29 NC
28 NC
27 I/O2
26 I/O1
25 I/O0
24 A0
23 A1
22 A2
21 A3
3005 ILL F22.2
30
A7
A6
5 4 3 2 32 31 29
6 1 28
A14
A13
A5 7
27 A8
A4
A3
8 26
9
X28LC512
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20 21
I/O7
3005 ILL F03
PLCC
30
A6
A5
5 4 3 2 32 31 29
6 1 28
A8
A9
A4 7
27 A11
A3
A2
8 26
9
X28LC513
(TOP VIEW)
25
NC
OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
14
15 16 17 18 19 20 21
I/O6
3005 ILL F04.1
Characteristics subject to change without notice

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X28LC512/X28LC513
PIN DESCRIPTIONS
Addresses (A0–A15)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28LC512/513
through the I/O pins.
FUNCTIONAL DIAGRAM
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28LC512/513.
PIN NAMES
Symbol
A0–A15
I/O0–I/O7
WE
CE
OE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
3.3V ± 10%
Ground
No Connect
3005 PGM T01
A7–A15
X BUFFERS
LATCHES AND
DECODER
512K-BIT
E2PROM
ARRAY
A0–A6
Y BUFFERS
LATCHES AND
DECODER
CE
OE
WE
VCC
VSS
CONTROL
LOGIC AND
TIMING
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
3005 ILL F01
2

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X28LC512/X28LC513
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28LC512/513 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
5ms.
Page Write Operation
The page write feature of the X28LC512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28LC512/513 prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the source
address), but the page address (A7 through A15) for
each subsequent valid write cycle to the part during this
operation must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28LC512/513 provides the user two write opera-
tion status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O DP TB 5 4 3 2 1 0
RESERVED
TOGGLE BIT
DATA POLLING
3005 ILL F11
DATA Polling (I/O7)
The X28LC512/513 features DATA Polling as a method
to indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28LC512/
513, eliminating additional interrupt inputs or external
hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28LC512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3

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X28LC512/X28LC513
DATA Polling I/O7
Figure 2a. DATA Polling Bus Sequence
LAST
WE WRITE
CE
OE
VIH
I/O7
A0–A15
An
HIGH Z
VOL
An An
An
Figure 2b. DATA Polling Software Flow
WRITE DATA
VOH
X28LC512
READY
An An An
3005 ILL F12
DATA Polling can effectively halve the time for writing to
the X28LC512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The
software flow diagram in Figure 2b illustrates one method
of implementing the routine.
WRITES
COMPLETE?
NO
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
YES
NO
X28LC512
READY
3005 ILL F13
4

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X28LC512/X28LC513
The Toggle Bit I/O6
Figure 3a. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
* Beginning and ending state of I/O6 will vary.
Figure 3b. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
HIGH Z
*
X28LC512
READY
3005 ILL F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28LC512/513 memories that is frequently
updated. Toggle Bit Polling can also provide a method
for status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
COMPARE
OK?
YES
X28LC512
READY
NO
3005 ILL F15
5