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X4003/X4005
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead MSOP
BLOCK DIAGRAM
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Watchdog Timer, and Supply Voltage
Supervision. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
REV 1.1.3 4/30/02
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X4003/X4005
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
NC
NC
RESET
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN DESCRIPTION
Pin
(SOIC/DIP)
1
2
3
Pin
TSSOP
3
4
5
46
57
68
71
82
Pin
(MSOP)
2
3
4
5
6
1
Name
NC
NC
RESET/
RESET
VSS
SDA
SCL
WP
VCC
Function
No internal connections
No internal connections
Reset Output. RESET/RESET is an active LOW/HIGH, open
drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC rises
above the minimum VCC sense level for 250ms. RESET/
RESET goes active if the watchdog timer is enabled and SDA
remains either HIGH or LOW longer than the selectable
Watchdog time out period. A falling edge of SDA, while SCL
also toggles from HIGH to LOW followed by a stop condition
resets the watchdog timer. RESET/RESET goes active on
power up and remains active for 250ms after the power supply
stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data
into and out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector outputs.
This pin requires a pull up resistor and the input buffer is
always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while
SCL also toggles from HIGH to LOW follow by a stop condition
resets the watchdog timer. The absence of this procedure with-
in the watchdog time out period results in RESET/RESET going
active.
Serial Clock. The serial clock controls the serial bus timing for
data input and output.
Write Protect. WP HIGH prevents changes to the watchdog timer
setting.
Supply voltage
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X4003/X4005
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4003/X4005 activates a
power on reset circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to
stabilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When VCC exceeds the device VTRIP threshold value
for 200ms (nominal) the circuit releases RESET/
RESET, allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvol-
atile control bits in the control register determine the
watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
.6µs
SCL
.6µs
SDA
Start
Condition
Restart
Stop
Condition
Set VTRIP Level Sequence (VCC = desired VTRIP value)
WP VP = 15-18V
0 1 2 34 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SCL
SDA
A0h
01h 00h
VCC THRESHOLD RESET PROCEDURE
The X4003/X4005 is shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard VTRIP is not
exactly right, or if higher precision is needed in the
VTRIP value, the X4003/X4005 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher
voltage value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
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X4003/X4005
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to
the programming voltage VP. Then write data 00hto
address 01h. The stop bit following a valid write operation
initiates the VTRIP programing sequence. Bring WP
LOW to complete the operation.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new VTRIP voltage, apply the desired
VTRIP threshold voltage to the VCC pin and tie the WP
pin to the programming voltage VP. Then write 00h to
address 03h. The stop bit of a valid write operation ini-
tiates the VTRIP programming sequence. Bring WP
LOW to complete the operation.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V)
WP VP = 15-18V
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SCL
SDA
A0h
03h 00h
Figure 3. Sample VTRIP Reset Circuit
VTRIP
Adj.
4.7K
RESET/
RESET
18
27
3 X4003/05 6
45
VP
Adjust
Run
µC
SCL
SDA
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X4003/X4005
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC–50mV)
New VCC Applied =
Old VCC applied + Error
RESET pin
goes active?
YES
Error Emax
Measured VTRIP -
Desired VTRIP
-Emax < Error < Emax
DONE
NO
Error –Emax
Emax = Maximum Allowable VTRIP Error
Control Register
The control register provides the user a mechanism for
changing the watchdog timer settings. watchdog timer
bits are nonvolatile and do not change when power is
removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a control
register write operation. Only one data byte is allowed
for each register write operation. Prior to writing to the
control register, the WEL and RWEL bits must be set
using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register"
below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
REV 1.1.3 4/30/02
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Characteristics subject to change without notice. 5 of 18