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64K X40620
Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Three standard reset threshold settings. (3.1V/
2.6V, 3.1V/1.7V, 2.9V/2.3V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—RESET signal valid down to VCC=1V
• Watchdog Timer (150ms)
• Power On Reset (150ms)
• Low Power CMOS
—10µA typical standby current, watchdog on
—400µA typical standby current, watchdog off
• 64kbit 2-Wire Serial EEPROM
—1MHz serial interface speed
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.5 to 3.7V Power Supply Operation
• 8-Lead TSSOP package
DESCRIPTION
The X40620 combines several functions into one
device. The first is a dual voltage monitoring, power-on
reset control, watchdog timer and 64Kbit serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET active for a period of time.
This allows the power supply and system oscillator to
stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the set minimum Vtrip point. RESET is
active until VCC returns to proper operating level and
stabilizes.
A second voltage monitor circuit (V2MON) tracks the
unregulated supply to provide a power fail warning or
monitors different power supply voltage. When the
second monitored voltage drops below a preset
V2TRIP voltage. V2FAIL is active until V2 returns to
proper operating level and above the V2TRIP voltage.
Five common low voltage combinations are available,
however, Xicor’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
BLOCK DIAGRAM
WP
Write Control
Logic
SCL
SDA
Command
Decode
and
Control
Logic
HV Generation
Timing and Control
EEPROM Array
(64Kbits)
(VCC) Control Signal
Y Decoder
Data Register
Xicor, Inc. 2000 Patents Pending
9900-3003.5 4/24/00 EP
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET
+
- V2TRIP
+
- VTRIP
V2FAIL
V2MON
VCC
Characteristics subject to change without notice. 1 of 17

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X40620
PACKAGE/PINOUTS
VSS
WP
SDA
RESET
8L TSSOP
18
27
36
45
VCC
V2MON
SCL
V2FAIL
PIN NAMES
VSS
SDA
VCC
SCL
WP
V2MON
RESET
V2FAIL
Ground
Serial Data
Power
Serial Clock
Write Protect
Voltage monitor input
Low Voltage Detect Output
V2 Voltage Fail Output
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with other open drain or open col-
lector outputs. An open drain requires the use of a
pull-up resistor.
Write Protect (WP)
The WP pin should be tied HIGH at all time. (This WP
pin is reserved for internal factory testing only).
Reset Output (RESET)
RESET is an active LOW, open drain output which
goes active whenever VCC falls below the minimum
Vtrip sense level. It will remain active until VCC rises
above the minimum Vtrip sense level for 150ms.
RESET goes active if the Watchdog Timer is enabled
and there is no start bit before the end of the select-
able Watchdog time-out period. A serial start bit will
reset the Watchdog Timer. RESET also goes active on
power up at 1V and remains active for 150ms after the
power supply stabilizes.
V2 Voltage Fail Output (V2FAIL)
V2FAIL is an active LOW, open drain output which
goes active whenever V2MON falls below the mini-
mum V2trip sense level. It will remain active until
V2MON rises above the minimum V2MON sense level.
DEVICE OPERATION
Power On Reset
Application of power to the X40620 activates a Power
On Reset Circuit. This circuit goes active at 1V and
pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscil-
lator. When VCC exceeds the device VTRIP value for
200ms (nominal) the circuit releases RESET allowing
the processor to begin executing code.
Low Voltage VCC (V1) Monitoring
During operation, the X40620 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
When the internal low voltage detect circuitry senses
that VCC is low, the following happens:
– The RESET pin goes active.
– Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the circuitry does not
stop the nonvolatile store operation, but attempts to
complete the operation.
The low VCC threshold is typically set to 3.1V for a 2.5
to 3.7V operating range.
LOW VOLTAGE V2 MONITORING
The X40620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V2TRIP. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the VCC drops below 1V. It also remains active
until V2MON returns and exceeds V2TRIP by 0.2V
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X40620
When the internal low voltage detect circuitry senses
that V2MON is low, the V2FAIL pin goes active. Typi-
cally this would be used by the processor as an inter-
rupt to stop the execution of the code or to do
housekeeping in preparation for an impending power
failure.
The RESET and V2FAIL signals remain active until
VCC voltage drops below 1V. RESET remains active
until VCC returns and exceeds VTRIP for 200ms.
V2FAIL remains active until immediately after V2MON
returns and exceeds it’s minimum voltage.
Volt
Reg
OTP Mode
Enabled
Pin 1
VSS
WP
VCC
V2MON
SDA
SCL
RESET V2FAIL
Recommended Connection
µC
VCC
SCL
SDA
INTR
RESET
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the Start bit. The micropro-
cessor must send a start bit periodically to prevent a
RESET signal. The start bit must occur prior to the
expiration of the watchdog time-out period. The watch-
dog timer period is set at 150msec.
SERIAL MEMORY OPERATION
There are two primary modes of operation for the
X40620; READ and WRITE of the memory arrays.
The basic method of communication to the memory
areas of the device is established by generating a start
condition, then transmitting a command, followed by
the address. The user must perform ACK Polling to
determine the validity of the address, before starting a
data transfer (see Acknowledge Polling.)
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
If the X40620 is in a nonvolatile write cycle a “no ACK”
(SDA=HIGH) response will be issued in response to
loading of the command byte. If a stop is issued prior
to the start of a nonvolatile write cycle the write opera-
tion will be terminated and the part will reset and enter
into a standby mode.
The basic sequence is illustrated in Figure 1.
After each transaction is completed, the X40620 will
reset and enter into a standby mode.
Figure 1. X40620 Device Operation
Load Command Byte
Load 2 Byte Address
Read/Write
Data Bytes
TWC or Data ACK Polling
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X40620
Figure 2. Set VTRIP Level Sequence (VCC VTRIP)
VCC VTRIP
RESET
VP = 15V
0 1 23 4 56 7
01 23 4 56 7
01 23 4 56 7
01 23 4 56 7
SCL
SDA
D8h
00h
Figure 3. Set V2TRIP Level Sequence (VCC V2TRIP)
V2TRIP
V2MON
RESET
VP = 15V
01h
01h sets VCC
00h
0 1 23 4 56 7
01 23 4 56 7
01 23 4 56 7
01 23 4 56 7
SCL
SDA
D8h
00h 0Dh 00h
0Dh sets V2MON
Figure 4. Reset VTRIP Level Sequence (VCC > 3V, WEL is set.)
VCC VTRIP
RESET
VP = 15V
0 1 23 4 56 7
01 23 4 56 7
01 23 4 56 7
01 23 4 56 7
SCL
SDA
D8h
00h 03h 00h
03h resets VCC
Characteristics subject to change without notice. 4 of 17

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X40620
Figure 5. Reset V2TRIP Level Sequence (VCC > 3V, WEL is set.)
VCC VTRIP
RESET
VP = 15V
0 1 23 4 56 7
01 23 4 56 7
01 23 4 56 7
01 23 4 56 7
SCL
SDA
D8h
00h 03h
03h resets VCC
00h
VCC AND V2MON THRESHOLD RESET PROCEDURE
The X40620 is shipped with standard VTRIP and
V2TRIP voltages. These values will not change over
normal operating and storage conditions. However, in
applications where the standard thresholds are not
exactly right, or if higher precision is needed in the
threshold value, the X40620 trip points may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP,V2TRIP to a
higher voltage value. For example, if the current VTRIP
is 4.4V and the new VTRIP is 4.6V, this procedure will
directly make the change. If the new setting is to be
lower than the current setting, then it is necessary to
reset the trip point before setting the new value.
To set the new voltages, apply the desired VTRIP thresh-
old voltage to the VCC pin, the V2TRIP voltage to the
V2MON pin, then tie the RESET pin to the programming
voltage VP. Then, write data 01h or 0Dh at address
00h to program VTRIP, V2TRIP respectively. The stop
bit following a valid write operation initiates the pro-
gramming sequence. Bring RESET LOW to complete
the operation. Note: this operation also writes 01h or
0Dh to address 00h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP, the V2TRIP to
a “native” voltage level. For example, if the current
VTRIP is 4.4V and the new VTRIP must be 4.0V, then
the VTRIP must be reset. When the threshold is reset,
the new level is something less than 1.7V. This proce-
dure must be used to set the voltage to a lower value.
To reset the new VTRIP, V2TRIP voltage, apply the
desired VTRIP or V2TRIP threshold voltage to the
VCCor V2MON pin, respectively, and tie the RESET
pin to the programming voltage VP. Then write 03h or
0Fh to address 00h. The stop bit of a valid write opera-
tion initiates the programming sequence. Bring
RESET LOW to complete the operation. Note: this
operation also writes 03h or 0Fh to address 00h of the
EEPROM array.
Figure 6. Sample VTRIP Reset Circuit
VTRIP
Adj.
V2FAIL
RESET
V2TRIP
Adj.
4.7K
58
42
7 X40620 6
13
VP
Adjust
Run
µC
SCL
SDA
Characteristics subject to change without notice. 5 of 17