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Preliminary Information
64K X46402
Dual Voltage CPU Supervisor with 64K Password Protected EEPROM
FEATURES
• Dual Voltage Detection and Reset Assertion
—Low Vcc Monitor
—Low V2MON Monitor
—Low Vcc Block of EEPROM Writes
—RESET Signal Valid down to Vcc=1V
• Selectable Watchdog Timer
—150ms, 450ms, 1s, 5s, 10s, 20s, 1min, OFF
• Volatile Flag shows Watchdog/Low Voltage Reset
• 64kbit 2-wire Serial EEPROM
—1MHz Serial Interface speed
—64-Byte Page Write Mode
• Two 64-Byte OTP memory blocks
—Requires 64-bit OTP password to write
• Adjustable size Password Protected Array
—64 Bit Read and Write Array Passwords
—Non-password protected array area
• 8 count tamper counter for invalid passwords
• Operates at 2.5-3.7V
• 8L TSSOP package
DESCRIPTION
The X46402 combines several functions into one device.
The first is a dual voltage CPU supervisor plus 64Kbit
serial EEPROM memory with password protected write
and read operations. The size of the password protected
area is selectable by 3 control bits. A Write Protect (WP)
pin in conjunction with a WPEN bit provides hardware
OTP control of the configuration of the array. Password
protected areas require 64 bit read or write passwords
prior to access. The eighth illegal password entry
(regardless of the number of correct entries) sets an OTP
tamper bit. This bit is one of the 32 bits in the Device ID.
A secondary voltage monitor circuit activates a V2FAIL
pin when the secondary supply voltage drops below a
V2trip voltage. This circuit is primarily intended to detect
the immediate loss of the battery supply.
A low Vcc voltage detect circuit activates a RESET pin
when Vcc drops below a VTRIP voltage. This signal also
blocks read or write operations.
A watchdog timer with the time period controlled by three
bits provides several possible time out periods from
150ms to 1 minute.
Functional Diagram
WP
Write Control
Password Logic
HV Generation
Timing and Control
SCL
SDA
Command
Decode
and
Control
Logic
Write Password Area
(Bytes)
(64, 128, 256, 512,
2K, 4K, All, None)
No Password Area
Control
OTP array 1
OTP array 2
Passwords
(Vcc) Control Signal
Y Decoder
Data Register
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
9900-3003 5 1/11/00 CM
1
WATCHDOG
TIMER RESET
RESET &
WATCHDOG
TIMEBASE
POWER ON AND
LOW VOLTAGE
RESET
GENERATION
RESET
+
- V2TRIP
+
- VTRIP
V2FAIL
V2MON
Vcc
Characteristics subject to change without notice

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X46402
Preliminary Information
PACKAGE/PINOUTS
VSS
WP
SDA
RESET
8L TSSOP
18
27
36
45
VCC
V2MON
SCL
V2FAIL
PIN NAMES
VSS
SDA
VCC
SCL
WP
V2MON
RESET
V2FAIL
Ground
Serial Data
Power
Serial Clock
Write Protect
Voltage monitor input
Low Voltage Detect Output
V2 Voltage Fail Output
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with other open drain or open collector out-
puts. An open drain requires the use of a pull-up resistor.
Write Protect (WP)
The WP pin works in conjunction with a nonvolatile
WPEN bit to “lock” the setting of the Watchdog Timer
control and the memory write protect bits.
Reset Output (RESET)
RESET is an active LOW, open drain output which goes
active whenever Vcc falls below the minimum Vtrip sense
level. It will remain active until Vcc rises above the mini-
mum Vtrip sense level for 150ms. RESET goes active if
the Watchdog Timer is enabled and there is no start bit
before the end of the selectable Watchdog time-out
period. A serial start bit will reset the Watchdog Timer.
RESET also goes active on power up at 1V and remains
active for 150ms after the power supply stabilizes.
V2 Voltage Fail Output (V2FAIL)
V2FAIL is an active LOW, open drain output which goes
active whenever V2MON falls below the minimum V2trip
sense level. It will remain active until V2MON rises above
the minimum V2MON sense level.
DEVICE OPERATION
Power On Reset
Application of power to the X46402 activates a Power On
Reset Circuit. This circuit goes active at 1V and pulls the
RESET pin active. This signal prevents the system micro-
processor from starting to operate with insufficient volt-
age or prior to stabilization of the oscillator. When Vcc
exceeds the device VTRIP value for 200ms (nominal) the
circuit releases RESET allowing the processor to begin
executing code.
Low Voltage Monitoring
During operation, the X46402 monitors the VCC and
V2MON levels and compares these with internal, preset
voltages.
When the internal low voltage detect circuitry senses that
V2MON is low, the V2FAIL pin goes active. Typically this
would be used by the processor as an interrupt to stop
the execution of the code or to do housekeeping in prep-
aration for an impending power failure.
When the internal low voltage detect circuitry senses that
Vcc is low, the following happens:
—The RESET pin goes active.
—The Flag bit in the control register is set to zero.
—Communication to the device is interrupted and any
command is aborted. If a serial nonvolatile store is in
progress when power fails, the circuitry does not stop
the nonvolatile store operation, but attempts to com-
plete the operation.
The RESET and V2FAIL signals remain active until Vcc
voltage drops below 1V. RESET remains active until Vcc
returns and exceeds VTRIP for 200ms. V2FAIL remains
active until immediately after V2MON returns and
exceeds it’s minimum voltage.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the Start bit. The microprocessor
must send a start bit periodically to prevent a RESET sig-
nal. The start bit must occur prior to the expiration of the
watchdog time-out period. The state of three nonvolatile
control bits in the Control Register determines the watch-
dog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP
pin HIGH and setting the WPEN bit HIGH.
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X46402
Preliminary Information
Volt
Reg
OTP Mode
Enabled
Pin1
Vss
WP
Vcc
V2MON
SDA
SCL
RESET V2FAIL
Recommended Connection
µC
Vcc
SCL
SDA
INTR
RESET
ARCHITECTURE
Data Memory
This 64kbit memory array can be partitioned into pass-
word protected or non-password protected areas. When
password protected, the contents are readable after
sending a “Memory Read” password. The contents of a
password protected portion of the memory array are
writeable with a “Memory Write” Password. This array is
re-writable up to the limit of the EEPROM endurance.
OTP
The second section of memory consists of two 64-byte
arrays, each writable only once. These arrays are always
password protected. Reading from either of these arrays
requires the use of an “OTP Read” password. Both
arrays can be read with a single operation. Writing either
array requires an “OTP Write” Password. Writing more
than 64 bytes to each array results in the data “wrapping”
around and over-writing previous values.
Array
OTP Array 1
OTP Array 2
Address
0000h - 003Fh
0040h - 007Fh
Control Register
A password protected read or write array command at
address FFFFh reads or writes the Control Register.
Since the control register contains information relating to
the password protection, it is necessary to use the Array
passwords to access the control register.
The Control Register contains bits that control the watch-
dog timer and the hardware write protect features and is
formatted as follows:
7 6543210
WPEN FLB WD2 WD1 WD0 BL2 BL1 BL0
Write Protect Enable bit (WPEN)
The WP pin, in conjuction with a WPEN bit programmed
HIGH, provides Hardware Write Protection. This prevents
changes to the control register contents even with a valid
password. When either the WP pin or WPEN bit is LOW,
a 64 bit Array write array password is required to change
the contents of the control register. When both the WP
pin and the WPEN bit are HIGH, the Control Register
cannot be written.
Flag Bit
The flag bit is a volatile bit. It can be used to determine if
a reset condition was due to a power failure or watchdog
reset condition. If power fails (i.e. the internal low voltage
detect signal goes active), the bit is set to ’0’. This bit is
also set or reset by a Control Register write operation. A
watchdog reset does not change the state of the flag bit.
Watchdog Timer Control
The Watchdog time-out period is controlled by the bits
WD2, WD1, and WD0. See the following Table.
Table 1. Watchdog Time Control Bits
Control Register Bits
WD2 WD1 WD0
000
001
010
011
100
101
110
111
Watchdog Time-out
(Typical)
1 Second
450 Milliseconds
150 Milliseconds
Disabled
1 minute
20 seconds
10 seconds
5 seconds
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X46402
Password Protection Configuration
Portions of the memory array may be “locked”. This area
of memory is password protected and is defined by the
bits BL2, BL1 and BL0. For these protected areas it is
necessary to use a Read password to output data and an
“Array Write” Password to write data. This block lock
area is re-writable, by issuing the correct password.
Table 2. Password Protected Block Size Select
BL2
BL1
BL0
000
001
010
011
100
101
110
111
Password Protected
Addresses
(Use Password
Command)
None
0000h - 003Fh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
0000h - 07FFh
0000h - 0FFFh
0000h - 1FFFh
Non-Password
Protected Addresses
(Use Password or
No-Password Commands)
0000h - 1FFFh
0040h - 1FFFh
0080h - 1FFFh
0100h - 1FFFh
0200h - 1FFFh
0800h - 1FFFh
1000h - 1FFFh
None
SERIAL MEMORY OPERATION
There are four primary modes of operation for the
X46402; Protected READ and WRITE of the memory
and OTP arrays and unprotected Read and Write of non-
password protected areas of the memory array. Pro-
tected operations must be performed with one of four 8-
byte passwords.
The basic method of communication for the password
protected areas of the device is established by generat-
ing a start condition, then transmitting a command, fol-
lowed by the correct password. All parts will be shipped
from the factory with all passwords equal to ‘0’. The user
must perform ACK Polling to determine the validity of the
password, before starting a data transfer (see Acknowl-
edge Polling.) Only after the correct password is
accepted and a ACK polling has been performed, can
the data transfer occur.
Non-password protected areas of the memory array are
accessed in the same manner as access to password
protected areas, except the password and the password
acknowledge polling sequences are not required.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
Preliminary Information
If the X46402 is in a nonvolatile write cycle a “no ACK”
(SDA=HIGH) response will be issued in response to
loading of the command byte. If a stop is issued prior to
the start of a nonvolatile write cycle the write operation
will be terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
After each transaction is completed, the X46402 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
Password Protection
The X46402 requires a 64 bit write password to change
the contents of the control register or to write to a block
protected memory area. The X46402 also requires a 64
bit read password to output the contents of the block pro-
tected array or the control register. The block protection is
controlled by the [BL2:BL0] bits and allows the options
described in Table 2. If an area is block protected, it
needs a password prior to each read or write to the area.
The passwords cannot be read, even after the device
receives the correct password.
Figure 1. X46402 Device Operation (Password
Protected Areas)
LOAD COMMAND BYTE
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
LOAD 2 BYTE ADDRESS
READ/WRITE
DATA BYTES
Twc OR DATA ACK POLLING
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X46402
Figure 2. Set VTRIP Level Sequence (VCC VTRIP)
VCC
VTRIP
RESET
VP = 15V
0 1 2 34 5 6 7
0 1 2 34 5 6 7
SCL
SDA
D8h
00h
Figure 3. Set V2TRIP Level Sequence (VCC V2TRIP)
V2TRIP
V2MON
RESET
VP = 15V
0 1 2 34 5 6 7
0 1 2 34 5 6 7
SCL
SDA
D8h
00h
Figure 4. Reset VTRIP Level Sequence (Vcc > 3V, WEL is set.)
VCC
VTRIP
RESET
SCL
SDA
VP = 15V
0 1 2 34 5 6 7
0 1 2 34 5 6 7
D8h 00h
Preliminary Information
0 1 2 34 5 6 7
01h
01h sets Vcc
0 1 2 34 5 6 7
0Dh
0Dh sets V2MON
0 1 2 34 5 6 7
03h
03h resets Vcc
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