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4K
X5043/X5045
512 x 8 Bit
CPU Supervisor with 4K SPI EEPROM
FEATURES
• Selectable time out watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<10µA max standby current, watchdog off
—<2mA max active current during read
• 2.7V to 5.5V and 4.5V to 5.5V power supply
versions
• 4Kbits of EEPROM–1M write cycle endurance
• Save critical data with Block Lockmemory
—Protect 1/4, 1/2, all or none of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• 3.3MHz clock rate
• Minimize programming time
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead MSOP, 8-lead SOIC, 8-pin PDIP
—14-lead TSSOP
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscil-
lator to stabilize before the processor executes code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
1Kbits
1Kbits
2Kbits
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET/RESET
X5043 = RESET
X5045 = RESET
Power on and
VCC + Low Voltage
Reset
VTRIP
-
Generation
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X5043/X5045
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
8-Lead SOIC/PDIP/MSOP
CS/WDI
SO
WP
VSS
18
27
3 X5043/45 6
45
VCC
RESET/RESET
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
14-Lead TSSOP
1 14
2 13
3 12
4 X5043/45 11
5 10
69
78
VCC
RESET/RESET
NC
NC
NC
SCK
SI
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the fall-
ing edge of the clock input.
Chip Select (CS)
When CS is high, the X5043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X5043/45 will
be in the standby power mode. CS low enables the
X5043/45, placing it in the active power mode. It should
be noted that after power-up, a high to low transition on
CS is required prior to the start of any operation.
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043/45 are
disabled, but the part otherwise functions normally.
When WP is held high, all functions, including non vol-
atile writes operate normally. WP going low while CS is
still low will interrupt a write to the X5043/45. If the
internal write cycle has already been initiated, WP
going low will have no affect on a write.
Reset (RESET, RESET)
X5043/45, RESET/RESET is an active low/HIGH,
open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if the
Watchdog timer is enabled and CS remains either high
or low longer than the Watchdog time out period. A fall-
ing edge of CS will reset the watchdog timer.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
RESET/RESET
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
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X5043/X5045
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5043/X5045 activates a
Power On Reset Circuit. This circuit pulls the RESET/
RESET pin active. RESET/RESET prevents the sys-
tem microprocessor from starting to operate with insuf-
ficient voltage or prior to stabilization of the oscillator.
When VCC exceeds the device VTRIP value for 200ms
(nominal) the circuit releases RESET/RESET, allowing
the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5043/X5045 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the WDI input. The micropro-
cessor must toggle the CS/WDI pin periodically to
prevent an active RESET/RESET signal. The CS/WDI
pin must be toggled from HIGH to LOW prior to the
expiration of the watchdog time out period. The state of
two nonvolatile control bits in the Status Register
determines the watchdog timer period. The micropro-
cessor can change these watchdog bits. With no
microprocessor action, the watchdog timer control bits
remain unchanged, even during total power failure.
VCC Threshold Reset Procedure
The X5043/X5045 is shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard VTRIP is not
exactly right, or if higher precision is needed in the
VTRIP value, the X5043/X5045 threshold may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher volt-
age value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to
the programming voltage VP. Then send a WREN com-
mand, followed by a write of Data 00h to address 01h.
CS going HIGH on the write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Note: This operation also writes 00h to array address 01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value.)
WP VPE = 15-18V
CS
SCK
0 1 23 4 56 7
SI
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06h
WREN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
02h
Write
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8 Bits
01h
Address
00h
Data
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X5043/X5045
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the VTRIP voltage, apply at least 3V to the VCC
pin and tie the WP pin to the programming voltage VP.
Then send a WREN command, followed by a write of
Data 00h to address 03h. CS going HIGH on the write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address
03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15–18V)
WP VPE = 15-18V
CS
SCK
0 1 23 4 56 7
SI
06h
WREN
Figure 3. Sample VTRIP Reset Circuit
VTRIP
Adj.
VP
Adjust
Run
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8 Bits
02h
Write
03h
Address
18
2 X5043 7
3 X5045 6
45
4.7K
RESET
00h
Data
µC
SCK
SI
SO
CS
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X5043/X5045
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied
=
Old VCC Applied
- Error
Execute
Set VTRIP
Sequence
New VCC Applied
=
Old VCC Applied
- Error
Apply 5V to VCC
Decrement VCC
(VCC = VCC–10mV)
Execute
Reset VTRIP
Sequence
NO RESET pin
goes active?
YES
Error -Emax
Measured VTRIP
-Desired VTRIP
Error Emax
-Emax < Error < Emax
DONE
Emax = Maximum Desired Error
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x8 bits. The device fea-
tures a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that
controls the operation of the device. The instruction
code is written to the device via the SI input. There are
two write operations that requires only the instruction
byte. There are two read operations that use the
instruction byte to initiate the output of data. The
remainder of the operations require an instruction byte,
an 8-bit address, then data bytes. All instruction,
address and data bits are clocked by the SCK input. All
instructions (Table 1), addresses and data are trans-
ferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static,
allowing the user to stop the clock and then start it
again to resume operations where left off. CS must be
LOW during the entire operation.
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RSDR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 A8011
0000 A8010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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