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X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
—Re-program low VCC reset threshold voltage
using special programming sequence.
—Reset signal valid to VCC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lockmemory
—Block lock first or last page, any 1/4 or lower 1/2
of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
—16 byte page write mode
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Set Top Boxes
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
• Battery Powered Equipment
Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
BLOCK DIAGRAM
VCC
CS/WDI
SI
SO
SCK
WP
VTRIP
+
-
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
8Kbits
RESET (X5083)
X5083
Standard VTRIP Level
4.63V (+/-2.5%)
Suffix
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 21 for
more details
For Custom Settings, call Xicor.
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X5083
DESCRIPTION
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Super-
vision, and Block Lock Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
PIN CONFIGURATION
8-Lead TSSOP
RESET
VCC
CS/WDI
SO
18
2
3
X5083
7
6
45
SCK
SI
VSS
WP
fails to restart a timer within a selectable time out interval,
the device activates the RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC trip
point. RESET is asserted until VCC returns to the
proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold
for applications requiring higher precision.
8-Lead SOIC, PDIP
CS/WDI
SO
WP
VSS
18
27
3 X5083 6
45
VCC
RESET
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/ Pin
PDIP) TSSOP Name
Function
1 3 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high
impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in the active power mode. Prior to the
start of any operation after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET
going active.
2 4 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The
falling edge of the serial clock (SCK) clocks the data out.
5 7 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data
on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes
(Table 1), addresses and data MSB first.
6 8 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
3 5 WP Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited.
This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the
device operates normally.
4 6 VSS Ground
8 2 VCC Supply Voltage
7 1 RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the
minimum VCC sense level for 250ms. RESET goes active if the watchdog timer is enabled and
CS remains either HIGH or LOW longer than the selectable watchdog time out period.
A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about
1V and remains active for 250ms after the power supply stabilizes.
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X5083
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5083 activates a power on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator.
RESET active also blocks communication to the device
through the SPI interface. When VCC exceeds the
device VTRIP value for 200ms (nominal) the circuit
releases RESET, allowing the processor to begin exe-
cuting code. While VCC < VTRIP communications to the
device are inhibited.
Low Voltage Monitoring
During operation, the X5083 monitors the VCC level
and asserts RESET if supply voltage falls below a pre-
set minimum VTRIP. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition and terminates any SPI communi-
cation in progress. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
When VCC falls below VTRIP, any communications in
progress are terminated and communications are
inhibited until VCC exceeds VTRIP for tPURST.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time
out period. The state of two nonvolatile control bits in the
status register determine the watchdog timer period. The
microprocessor can change these watchdog bits with no
action taken by the microprocessor these bits remain
unchanged, even after total power failure.
VCC Threshold Reset Procedure
The X5083 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X5083 threshold may be adjusted. The procedure is
described below, and uses the application of a high
voltage control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher
voltage value. For example, if the current VTRIP is 4.4V
and the new VTRIP is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to
the programming voltage VP. Then send a WREN com-
mand, followed by a write of Data 00h to address 01h.
CS going HIGH on the write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Note: This operation also writes 00h to array address
01h.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP value)
WP VP = 15-18V
CS
SCK
0 1 23 4 56 7
SI
06h
WREN
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
02h
Write
16 Bits
0001h
Address
00h
Data
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X5083
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new VTRIP voltage, apply the desired
VTRIP threshold voltage to the Vcc pin and tie the WP
pin to the programming voltage VP. Then send a WREN
command, followed by a write of data 00h to address
03h. CS going HIGH on the write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Note: This operation also writes 00h to array address
03h.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15–18V)
WP VP = 15-18V
CS
SCK
0 1 23 4 56 7
SI
06h
WREN
Figure 3. Sample VTRIP Reset Circuit
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
02h
Write
16 Bits
0003h
Address
VTRIP
Adj.
VP
Adjust
Run
18
27
3 X5083 6
45
4.7K
RESET
00h
Data
µC
SCK
SI
SO
CS
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X5083
Figure 4. VTRIP Programming Sequence
New VCC Applied =
Old VCC Applied + Error
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
NO RESET pin
goes active?
YES
Error –Emax
Emax = Maximum Desired Error
Measured VTRIP -
Desired VTRIP
Error Emax
–Emax < Error < Emax
DONE
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus
activity within the user selectable time out period or the
supply voltage falls below a preset minimum VTRIP.
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
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Characteristics subject to change without notice. 5 of 21