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APPLICATION NOTES
AVA I L A B L E
X68C7AN562S• ALNI6C4 •®ANE662 • AN74
SLIC X68C75 SLIC® E2 Microperipheral
Port Expander and E2 Memory
FEATURES
• Highly Integrated Microcontroller Peripheral
—8K x 8 E2 Memory
—2 x 8 General Purpose Bidirectional I/O Ports
—16 x 8 General Purpose Registers
—Integerated Interrupt Controller Module
—Internal Programmable Address Decoding
• Self Loading Integrated Code (SLIC)
—On-Chip BIOS and Boot Loader
—IBM/PC Based Interface Software(XSLIC)
• Concurrent Read During Write
—Dual Plane Architecture
• Isolates Read/Write Functions Between
Planes
• Allows Continuous Execution Of Code
From One Plane While Writing In The
Other Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family of
Microcontrollers
• Software Data Protection
—Protect Entire Array During Power-up/-down
• Block Lock™ Data Protection
—Set Write Lockout in 1K Blocks
• Toggle Bit Polling
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
• 60mA Active
• 100µA Standby
• PDIP, PLCC, and TQFP Packaging Available
DESCRIPTION
The X68C75 is a highly integrated peripheral for the
68HC11 family of microcontrollers. The device inte-
grates 8K-bytes of 5V byte-alterable nonvolatile memory,
2 bidirectional 8-bit ports, 16 general purpose registers,
programmable internal address decoding and a multi-
plexed address and data bus.
The 5V byte-alterable nonvolatile memory can be used
as program storage, data storage, or a combination of
both. The memory array is separated into two 4K-byte
sections which allows read accesses to one section
while a write operation is taking place in the other
section. The nonvolatile memory also features Software
Data Protection to protect the contents during power
transitions, and an advanced Block Protect register
which allows individual blocks of the memory to be
configured as read-only or read/write.
PIN CONFIGURATIONS
DIP
RESET
A12
WC
SEL
STRA
A15
NC
A14
A13
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
X68C75
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
R/W
AS
A8
A9
A11
NC
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
NC
E
A10
CE
A/D7
A/D6
A/D5
2899 ILL F01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
2899-2.1 4/11/97 T0/C0/D1 SH
PLCC
TQFP
INDEX
CORNER
A14
A13
PA7
PA6
PA5
PA44
PA3
33
PA2
PA1
PA0
A/D0
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 X68C75 35
12 SLIC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A11
IRQ
STRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
2899 ILL F02.3
Concurrent Read During Write, Block Lock, and SLIC® E2 are registered trademarks of Xicor, Inc.
1 Characteristics subject to change without notice

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X68C75 SLIC® E2
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X68C75 is accomplished through the
multiplexed address/data bus of the 68HC11 type con-
trollers. An internal programmable address decoder
maps the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X68C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X68C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 68HC11 microcontroller. The
reading of data from the chip is controlled by the
R/W and E clock signals.
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
the falling edge of AS latches the address present on the
FUNCTIONAL DIAGRAM
address bus into the X68C75, and the falling edge of E
clock latches the data to be written.
The nonvolatile memory of the X68C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X68C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X68C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the nonvolatile memory array to be
treated as 8 independent sections of 1K-bytes. Each of
these sections can be independently enabled for write
operations. This allows segmentation of the memory
contents into writable and non-writable sections, thereby,
allowing certain sections of the device to be secured so
that updates can only occur in a controlled environ-
ment. (e.g. in an automotive application, only at an
authorized service center). The Block Protect configu-
ration is stored in a nonvolatile register, ensuring that
the configuration data will be maintained after the
device is powered-down.
A0–A15
ADDRESS
LATCH
I/O0–I/O7
I/O
BUFFER
&
LATCH
CE
R/W
E
AS
SEL
WC
RESET
IRQ
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
DATA I/O BUS
RIGHT PLANE
DECODE
16 X 8
GENERAL
PURPOSE
REGISTERS
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
PORT
A
PORT
B
PORT SELECT
SDP
DECODE
MEM. MAP
CONFIG
REGISTER
PORT
SPECIAL
FUNCTION
REGISTERS
2899 ILL F03
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X68C75 SLIC® E2
The X68C75 write control input, serves as an external
control over the completion of a previously initiated page
load cycle.
The X68C75 also features the industry standard 5V E2
memory characteristics such as byte or page mode write
and Toggle Bit Polling.
Read
A HIGH to LOW transition on AS latches the address;
the data will be output on the AD pins when E clock and
R/W are HIGH (tACC).
Write
A write is performed by latching the address on the
falling edge of AS. The R/W signal LOW while E clock is
HIGH initiates a write cycle. The valid data must be
present on AD0-AD7 prior to an E clock HIGH to LOW
transition. The data will be latched into the X68C75 on
the falling edge of E clock.
Page Write Operation
The X68C75 supports page mode write operations. This
allows the microcontroller to write from one to thirty-two
bytes of data to the X68C75. Each individual write within
a page write operation must conform to the byte write
timing requirements. The rising edge of E clock starts a
timer delaying the internal programming cycle 100µs,
therefore, each successive write operation must begin
within 100µs of the last byte written. The waveform
on page 19 illustrates the sequence and timing
requirements.
Toggle Bit Polling
Because the X68C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
PIN DESCRIPTIONS
PIN NAME
I/O DESCRIPTION
A15–A8
AD7–AD0
AS
CE
E
IRQ
PA7–PA0
PB7–PB0
R/W
RESET
SEL
STRA, STRB
WC
I Non-multiplexed high-order Address line inputs for the upper byte of the address. The addresses are
latched when AS makes a HIGH to LOW transition.
I/O Multiplexed lower-order Address and DATA lines. The addresses are latched when AS makes a
HIGH to LOW transition.
I Address Strobe input is used to latch the addresses present on the address lines A15–A8 and AD7
AD0 into the device. The addresses are latched when AS transitions from HIGH to LOW.
I The device select (CE) is an active HIGH input. This signal has to be asserted prior to AS HIGH to
LOW transition in order to generate a valid internal device select signal. Holding this pin LOW and
AS LOW will place the device in standby mode. The ports stay active at all times.
I The E clock is the bus frequency clock input, and is used as a data timing reference signal. When
the E clock is LOW, the addresses are latched by HIGH to LOW transition on the AS pin. The E
clock HIGH cycle is used for data transfers.
O The IRQ is an open-drain output. It can be configured to signal latching of new data into the ports,
and completion of an E2 memory write cycle.
I/O The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the
AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select the port A I/O mode.
I/O The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the
BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select the port B I/O mode.
I The R/W signal indicates the direction of data transfers. During phase 2 (HIGH cycle) of the E clock,
the R/W is HIGH for a read, and LOW for a write cycle.
I RESET is used to initialize the internal static registers and has no effect on the E2 memory opera-
tions. The default active level is LOW, but it can be reconfigured in EEM register.
I The SEL input should be LOW for the device to be selected. This input is normaly tied to VSS.
I/O The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid
transition on their strobe pins will latch into their Port Data Register the data present at the port input
pins. Writing to an output port Data Register generates a pulse of fixed duration on its corresponding
strobe pin. The output data presented at the output pins stay valid until the next data is written to the
output port data register.
I WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to
disable writes to the E2 memory. Taking the WC HIGH prior to tBLC (100µs; the time delay from the
last write cycle to the start of internal programming cycle) will inhibit the write operation.
2899 PGM T01.1
3

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X68C75 SLIC® E2
determine the early completion of a write cycle. During
the internal programming cycle, I/O6 will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
internal cycle is complete, the toggling will cease and the
device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A12 during a write must match the state of
A12 during polling.
DATA PROTECTION
The X68C75 provides two levels of data protection
through software control. There is a global software data
protection feature similar to the industry standard for
E2PROMs and a new Block Lock Protect write lockout
protection providing a secondary level data security
option.
Figure 1. Toggle Bit Polling E Control
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C75 READY FOR
NEXT OPERATION
CE
AS
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN
ADDR
E
R/W
2899 ILL F05
4

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X68C75 SLIC® E2
Software Data Protection
Software Data Protection (SDP) can be employed to
protect the entire array against inadvertent writes during
power-up/power-down operations. The X68C75 is
shipped from the factory with SDP enabled. With SDP
enabled, inadvertent attempts to write to the X68C75 will
be blocked.
The system can still write data, but only when the write
operation (page or byte) is preceded by the three-byte
command sequence. All write operations, both the com-
mand sequence and any data write operations must
conform to the page write timing requirements.
The SDP mode is also enabled anytime one of the
nonvolatile configuration registers are modified. These
include writing to EE map, SFR map, and BPR.
Block Lock Protect Write Lockout
The X68C75 provides a second level of data security
referred to as Block Lock Protect write lockout (or Block
Protection). This is accessed through an extension of
the SDP command sequence. Block Protect allows the
user to lockout writes to 1K x 8 blocks of memory. Unlike
SDP which prevents inadvertent writes, but still allows
Figure 2. Writing with SDP Enabled
AA b2 b1 b0 P 555
easy system access to writing the memory, Block Pro-
tect will lockout all attempts unless it is specifically
disabled by issuing the deactivation sequence. This
feature can be used to set a higher level of protection in
a system where a portion of the memory is used to store
the system kernel and protect it from the application
programs residing in the other blocks.
Setting write lockout is accomplished by writing a five-
byte command sequence opening access to the Block
Protect Register (BPR). After the fifth byte is written, the
user writes to the BPR, selecting which blocks to protect
or unprotect. All write operations, both the command
sequence and writing the data to the BPR, must conform
to the page write timing requirements. It should be noted
that accessing the BPR automatically sets the upper
level SDP. If for some reason the user does not want
SDP enabled, they may reset it using the normal reset
command sequence. This will not affect the state of the
BPR and any 1K x 8 blocks that were set to the write
lockout state will remain in the write lockout state.
Figure 3. Sequence to Deactivate
Software Data Protection
AA b2 b1 b0 P 555
55 b2 b1 b0 P AAA
55 b2 b1 b0 P AAA
A0 b2 b1 b0 P 555
A0 b2 b1 b0 P 555
Perform Byte or Page
Write Operations
AA b2 b1 b0 P 555
80 b2 b1 b0 P AAA
Delay of tWC
Delay of tWC
Exit Routine
2899 ILL F05B
b2
b1
b0
Reference the A15–A13
setting in EEM register
P = Address bit (A12) of the
updated memory plane.
Exit Routine
2899 ILL F05C
b2
b1
b0
Reference the A15–A13
setting in EEM register
P = Address bit (A12) of the
memory plane not being read.
5