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APPLICATION NOTE
A V A I LABLE
AN83 • Development Tools XK76C
Password Access Security Supervisor
4K
X76F041
4 x 128 x 8 Bit
PASSTM SecureFlash
FEATURES
• 64-Bit Password Security
• Three Password Modes
—Secure Read Access
—Secure Write Access
—Secure Configuration Access
• Programmable Configuration
—Read, Write and Configuration Access
Passwords
—Multiple Array Access/Functionality
—Retry Register/Counter
• 8 Byte Sector Write
• (4) 1K Memory Arrays
• ISO Response to Reset
• Low Power CMOS
—50µA Standby Current
—3mA Active Current
• 1.8V to 3.6V or 5V “Univolt” Read and Program
Power Supply Versions
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
—ESD Protection: 2000V on All Pins
DESCRIPTION
The X76F041 is a password access security supervisor
device, containing four 128 x 8 bit SecureFlash arrays.
Access can be controlled by three 64-bit programmable
passwords, one for read operations, one for write opera-
tions and one for device configuration.
The X76F041 features a serial interface and software
protocol allowing operation on a simple two wire bus. The
bus signals are a clock input (SCL) and a bidirectional
data input and output (SDA). Access to the device is con-
trolled through a chip select input (CS), allowing any
number of devices to share the same bus.
The X76F041 also features a synchronous response to
reset; providing an automatic output of a pre-configured
32-bit data stream conforming to the ISO standard for
memory cards.
The X76F041 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per sector and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
CS
SCL
SDA
RETRY
COUNTER
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7002-2.2 4/30/97 T3/C0/D0 SH
CHIP
ENABLE
DATA
TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY AND
PASSWORD VERIFICATION
LOGIC
ISO RESET RESPONSE
DATA REGISTER
CONFIGURATION
REGISTER
1
000–07F
080–0FF
100–17F
180–1FF
(4) 16 x 64
SECUREFLASH
ARRAYS
7002 ILL F01
Characteristics subject to change without notice

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X76F041
PIN DESCRIPTION
Serial Data Input/Output (SDA)
SDA is a true three state serial data input/output pin.
During a read cycle, data is shifted out on this pin.
During a write cycle, data is shifted in on this pin. In all
other cases this pin is in a high impedance state.
Serial Clock (SCL)
The Serial Clock controls the serial bus timing for data
input and output.
Chip Select (CS)
When CS is HIGH, the X76F041 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway the X76F041 will be in the
standby power mode. CS LOW enables the X76F041,
placing it in the active power mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed HIGH
while CS is LOW the X76F041 will output 32 bits of
fixed data which conforms to the ISO standard for
“synchronous response to reset”. CS must remain
LOW and the part must not be in a write cycle for the
response to reset to occur. If at any time during the
response to reset CS goes HIGH, the response to
reset will be aborted and the part will return to the
standby mode.
PIN CONFIGURATION
DIP/SOIC
VCC
RST
SCL
NC
18
27
X76F041
36
45
VSS
CS
SDA
NC
Symbol
CS
SDA
RST
SCL
VSS
VCC
NC
7002 ILL F02
Description
Chip Select Input
Serial Data Input/Output
Reset Input
Serial Clock Input
Ground
Supply Voltage
No Connect
7002 FRM T01
2

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X76F041
DEVICE OPERATION
There are three primary modes of operation for the
X76F041; READ, WRITE and CONFIGURATION. The
READ and WRITE modes may be performed with or
without an 8-byte password. The CONFIGURATION
mode always requires an 8-byte password.
The basic method of communication is established by
first enabling the device (CS LOW), generating a start
condition and then transmitting a command and address
field followed by the correct password (if configured to
require a password). All parts will be shipped from the
factory in the non-password mode. The user must per-
form an ACK Polling routine to determine the validity of
the password and start the data transfer (see Acknowl-
edge Polling). Only after the correct password is
accepted and an ACK Polling has been performed can
the data transfer occur.
To ensure correct communication, RST must remain
LOW under all conditions except when initiating a
“Response to Reset sequence”.
Figure 1. X76F041 Device Operation
LOAD
COMMAND+HIGH ORDER ADDRESS
BYTE
LOAD
LOW ORDER ADDRESS / CONFIGURATION INSTRUCTION
BYTE
LOAD 8–BYTE PASSWORD
(IF APPLICABLE)
VERIFY PASSWORD ACCEPTANCE BY USE
OF ACK POLLING (IF APPLICABLE)
READ / WRITE
DATA BYTES
7002 ILL F03
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F041 is in a nonvolatile write cycle a “no ACK”
(SDA HIGH) response will be issued in response to load-
ing of the command + high order address byte. If a stop
condition is issued prior to the nonvolatile write cycle the
write operation will be terminated and the part will reset
and enter into a standby mode.
The basic sequence is illustrated in Figure 1.
After each transaction is completed, the X76F041 will
reset and enter into a standby mode. This will also be the
response if an attempt is made to access any limited
array.
Password Registers
The three passwords, Read, Write and Configuration
are stored in three 64 bit Write Only registers as illus-
trated in figure 2.
Figure 2. Password Registers
63
64 BIT WRITE PASSWORD
0
64 BIT READ PASSWORD
64 BIT CONFIGURATION PASSWORD
7002 ILL F04
Device Configuration
Five 8-Bit configuration registers are used to configure
the X76F041. These are shown in figure 3.
Figure 3. Configuration Registers
63 0
ACR1 ACR2 CR RR RC RES RES RES
RESERVED
RETRY COUNTER
RETRY REGISTER
CONFIGURATION REGISTER
ARRAY CONTROL REGISTER 2
ARRAY CONTROL REGISTER 1
7002 ILL F04B
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X76F041
Array Control
The four 1K arrays, are each programmable to different
levels of access and functionality. Each array can be pro-
grammed to require or not require the read/write pass-
words. The functional options are:
• Read and Write Access.
• Read access with all write operations locked out.
• Read access and program only (writing a “1” to a
“0”). If an attempt to change a “0” to a “1” occurs the
X76F041 will reset, issue a “no ACK” and enter the
standby power mode.
• No read or write access to the memory. Access only
through use of the configuration password.
Array Map
First ‘1k’
Second ‘1k’
Third ‘1k’
Fourth ‘1k’
Addresses 000
Addresses 080
Addresses 100
Addresses 180
07F (hex)
0FF (hex)
17F (hex)
1FF (hex)
High-order
Addresses
7002 ILL F04A
8 Bit Array Control Register 1
SECOND 1K
X2 Y2 Z2 T2
ACCESS
MSB
FUNCTION
FIRST 1K
X1 Y1 Z1 T1
ACCESS
FUNCTION
LSB
7002 ILL F05A
8 Bit Array Control Register 2
UPPER 1K
X4 Y4 Z4 T4
ACCESS
MSB
FUNCTION
THIRD 1K
X3 Y3 Z3 T3
ACCESS
FUNCTION
LSB
7002 ILL F05B
Functional Bits
ZT
00
10
01
11
FUNCTIONALITY
READ AND WRITE UNLIMITED
READ ONLY, WRITE LIMITED
PROGRAM & READ ONLY,
ERASE LIMITED
NO READ OR WRITE, FULLY
LIMITED
7002 FRM T02
Access Bits
XY
READ
PASSWORD
WRITE
PASSWORD
0 0 NOT REQUIRED NOT REQUIRED
1 0 NOT REQUIRED REQUIRED
0 1 REQUIRED NOT REQUIRED
1 1 REQUIRED
8-Bit Configuration Register
REQUIRED
7002 FRM T03
MSB
LSB
UA1 UA2 1
0 RCR RCE 0
0
RESERVED
RETRY COUNTER ENABLE
RETRY COUNTER RESET
RESERVED
RESERVED
UNAUTHORIZED ACCESS BIT 2
UNAUTHORIZED ACCESS BIT 1
7002 ILL F06
Unauthorized Access Bits (UA1, UA2):
10
Access is forbidden if retry register equals the retry
counter (provided that the retry counter is enabled) and
no further access of any kind will be allowed.
0 1, 0 0, 1 1
Only configuration operations are allowed if the retry reg-
ister equals the retry counter (provided that the retry
counter is enabled).
Retry Counter Reset Bit (RCR):
If the retry counter reset bit is a “1” then the retry counter
will be reset following a correct password, provided the
retry counter is enabled.
If the retry counter reset bit is a “0” then the retry counter
will not be reset following a correct password, provided
the retry counter is enabled.
Retry Counter Enable Bit (RCE):
If the Retry counter enable bit is a “1”, then the retry
counter is enabled. An initial comparison between the
retry register and retry counter determines whether the
number of allowed incorrect password attempts has
been reached. If not, the protocol continues and in case
of a wrong password, the retry counter is incremented by
one. If the password is correct then the retry counter will
either be reset or unchanged, depending on the reset bit.
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X76F041
The retry register must have a higher value than the retry
counter for correct device operation. If the retry counter
value is larger than the retry register and the retry
counter is enabled, the device will wrap around allowing
up to an additional 255 incorrect access attempts.
If the Retry counter enable bit is a “0”, then the retry
counter is disabled.
Retry Register/Counter
Both the retry register and retry counter are accessible in
the configuration mode and may be programmed with a
value of 0 to 255.
The difference between the retry register and the retry
counter is the number of access attempts allowed, there-
fore the retry counter must be programmed to a smaller
value than the retry register to prevent wrap around.
Figure 4. Data Validity During Write
DEVICE PROTOCOL
The X76F041 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a mas-
ter and the device being controlled is the slave. The mas-
ter will always initiate data transfers, and provide the
clock for both transmit and receive operations. Therefore,
the X76F041 will be considered a slave in all applica-
tions.
Start Condition
All commands except for response to reset are preceded
by the start condition, which is a HIGH to LOW transition
of SDA when SCL is HIGH. The X76F041 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
has been met.
SCL
SDA
Figure 5. Definition of Start and Stop
DATA STABLE DATA
CHANGE
SCL
7002 ILL F07
SDA
START BIT
STOP BIT
7002 ILL F08
NOTE: The part requires the SCL input to be LOW during non-active periods of operation. In other words, the SCL will need to be LOW prior to
any START condition and LOW after a STOP condition.This is also reflected in the timing diagram.
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