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1K
X76F100
128 x 8 Bit
Secure SerialFlash
FEATURES
• 64-bit password security
• One array (112-bytes) two passwords (16-bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (rst input)
• 8-byte sector Write Mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—3.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead PDIP, SOIC, MSOP, and smart car module
DESCRIPTION
The X76F100 is a Password Access Security Supervi-
sor, containing one 896-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F100 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F100 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F100 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
CS
SCL
SDA
Interface
Logic
RST
Chip Enable
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
Reset
Response Register
8K Byte
SerialFlash Array
Array 0
(Password Protected)
32 Byte
SerialFlash Array
Array 1
(Password Protected)
Retry Counter
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X76F100
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Select (CS)
When CS is high, the X76F100 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F100 will be in
standby mode. CS low enables the X76F100, placing it
in the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F100 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 7. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state.
The response to reset is “mask programmable” only!
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
If the X76F100 is in a nonvolatile write cycle a “no
ACK” (SDA=High) response will be issued in response
to loading of the command byte. If a stop is issued prior
to the nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
VCC
VSS
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
DEVICE OPERATION
The X76F100 memory array consists of fourteen
8-byte sectors. Read or write access to the array
always begins at the first address of the sector. Read
operations then can continue indefinitely. Write opera-
tions must total 8-bytes.
There are two primary modes of operation for the
X76F100; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) Only after the cor-
rect password is accepted and a ACK polling has been
performed, can the data transfer occur.
VCC
NC
NC
VSS
VSS
CS
SDA
NC
PDIP
18
27
36
45
SOIC
18
27
36
45
RST
SCL
SDA
CS
VCC
RST
SCL
NC
VSS
NC
CS
SDA
MSOP
18
27
36
45
VCC
NC
RST
SCL
Smart Card
VCC
RST
SCL
NC
GND
CS
SDA
NC
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X76F100
After each transaction is completed, the X76F100 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Figure 1. X76F100 Device Operation
Load Command/Address Byte
Load 8-Byte
Password
Verify Password
Acceptance by
Use of Ack Polling
Read/Write
Data
Bytes
Retry Counter
The X76F100 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of
the passwords are cleared to “0”. If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
Device Protocol
The X76F100 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F100 will be considered a
slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F100 continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition is met.
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F100 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F100 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
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X76F100
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Table 1. X76F100 Instruction Set
Command after Start
1 0 0 S3 S2 S1 S00
1 0 0 S3 S2 S1 S0 1
11111100
11111110
01010101
Stop Condition
Command Description
Sector Write
Sector Read
Change Write Password
Change Read Password
Password ACK Command
Password Used
Write
Read
Write
Write
None
Illegal command codes will be disregarded. The part
will respond with a “no-ACK” to the illegal byte and
then return to the standby mode. All write/read opera-
tions require a password.
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in Figure 4. The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a
sector and eight bytes must be transferred. After the
last byte to be transferred is acknowledged a stop con-
dition is issued which starts the nonvolatile write cycle.
If more or less than 8-bytes are transferred, the data in
the sector remains unchanged.
ACK Polling
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F100 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8-bits (1st
byte of the protocol.) If the X76F100 is still busy with
the nonvolatile write operation, it will issue a “no-ACK”
in response. If the nonvolatile write operation has com-
pleted, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
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X76F100
Data ACK Polling Sequence
Write Sequence
Completed
Enter ACK Polling
Issue START
Issue New
Command Code
Password ACK Polling Sequence
Password Load
Completed
Enter ACK Polling
Issue START
Issue Password
ACK Command
ACK
returned?
YES
PROCEED
NO
ACK
returned?
YES
PROCEED
NO
After the password sequence, there is always a nonvol-
atile write cycle. This is done to discourage random
guesses of the password if the device is being tam-
pered with. In order to continue the transaction, the
X76F100 requires the master to perform a password
ACK polling sequence with the specific command code
of 55h. As with regular Acknowledge polling the user
can either time out for 10ms, and then issue the ACK
polling once, or continuously loop as described in the
flow.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the password ACK polling sequence is
over.
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the
password is incorrect until the 10ms write cycle time
has elapsed.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the
read command. Once the password has been acknowl-
edged data may be read from the sector. An acknowl-
edge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector,
but may stop at any time. Random accesses to the
array are not possible. Continuous reading from the
array will return data from successive sectors. After
reading the last sector in the array, the address is auto-
matically set to the first sector in the array and data can
continue to be read out. After the last bit has been
read, a stop condition is generated without sending a
preceding acknowledge.
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