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128K
X76F128
16Kx8+64x8
Secure SerialFlash
FEATURES
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 16384 Byte+64 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 64 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
—SmartCard Module
—TQFP Package
DESCRIPTION
The X76F128 is a Password Access Security Supervisor,
containing one 131072-bit Secure SerialFlash array and
one 512-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F128 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F128 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F128 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7052 10/7/97 T0/C0/D0 SH
CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
1
16K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
64 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7052 FM 01
Characteristics subject to change without notice

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X76F128
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During a
write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Chip Enable (CS)
When CS is high, the X76F128 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F128 will be in
standby mode. CS low enables the X76F128, placing it in
the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F128 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to
occur. See Figure 11. If at any time during the response
to reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
DEVICE OPERATION
There are two primary modes of operation for the
X76F128; Protected READ and protected WRITE.
Protected operations must be performed with one of four
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW), gen-
erating a start condition, then transmitting a command,
followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F128 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
Description
CS Chip Select Input
SDA
Serial Data Input/Output
SCL Serial Clock Input
RST
Reset Input
Vcc Supply Voltage
Vss Ground
NC No Connect
7052 FM T01
PIN CONFIGURATION
VCC
GND
Smart Card
RST
CS
SCL SDA
NC NC
7052 FM 02
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
CS
SDA
1
2
3
4
5
6
7
8
9
10
11
12
36 VCC
35 NC
34 NC
33 NC
32 NC
31 NC
30 NC
29 NC
28 NC
27 NC
26 RST
25 SCL
After each transaction is completed, the X76F128 will
reset and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
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X76F128
Figure 1. X76F128 Device Operation
LOAD COMMAND BYTE
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF PASSWORD ACK POLLING
LOAD 2 BYTE ADDRESS
READ/WRITE
DATA BYTES
Twc OR DATA ACK POLLING
7052 FM 03
Retry Counter
The X76F128 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, all memory areas are cleared and the device is
locked by preventing any read or write array password
matches. The passwords are unaffected. If a correct
password is received prior to retry counter overflow, the
retry counter is reset and access is granted. In order to
reset the operation of a locked up device, a special reset
command must be used with a RESET PASSWORD.
Device Protocol
The X76F128 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
a receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F128 will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F128 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts
are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F128 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F128 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
RESET DEVICE Command
The RESET DEVICE command is used to clear the retry
counter and reactivate the device. When the RESET
DEVICE command is used prior to the retry counter
overflow, the retry counter is reset and no arrays or pass-
words are affected. If the retry counter has overflowed, all
memory areas are cleared and all commands are
blocked and the retry counter is disabled. Issuing a valid
RESET DEVICE command (with reset password) to the
device resets and re-enables the retry counter and re-
enables the other commands. Again, the passwords are
not affected.
RESET PASSWORD Command
A RESET PASSWORD command will clear both arrays
and set all passwords to all zero.
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X76F128
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
7052 FM 04
SCL
SDA
Start Condition
Stop Condition
7052 FM 05
Table 1. X76F128 Instruction Set
1st Byte
after Start
1st Byte
after
Password
2nd Byte
after
Password
1000 0000 High Address Low address
1000 1000 High Address Low address
1001 0000 High Address Low address
1001 1000 High Address Low address
1010 0000 0000 0000 0000 0000
1010 1000 0000 0000 0000 0000
1011 0000 0000 0000
1011 1000 0000 0000
0000 0000
0000 0000
1100 0000 0000 0000
1110 0000 not used
0000 0000
not used
1110 1000 not used
not used
1111 0000
not used
All the rest
not used
Command Description
Read (Array 0)
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
RESET PASSWORD Command
RESET DEVICE Command
ACK Polling command (Ends Password operation)
Reserved
Password
used
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Reset
Reset
None
7052 FM T04
Notes: Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
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X76F128
PROGRAM OPERATIONS
Sector Programming
The sector program mode requires issuing the 8-bit write
command followed by the password, password Ack com-
mand, the address and then the data bytes transferred
as illustrated in figure 4. Up to 64 bytes may be trans-
ferred. After the last byte to be transferred is acknowl-
edged a stop condition is issued which starts the
nonvolatile write cycle.
Figure 4. Sector Programming
SDA S
COMMAND
Write
Password
7
If ACK, Then
Password Matches
ACK POLLING
COMMAND
S
Write
Password
0
Wait tWC
OR
Repeated
ACK Polling
Command
Data 0
...
Data 63
Wait tWC
S Data ACK Polling
7052 FM 07
5