V62C1162048L-70T.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 V62C1162048L-70T 데이타시트 다운로드

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Features
• Low-power consumption
- Active: 35mA ICC at 70ns
- Stand-by: 10 µA (CMOS input/output)
2 µA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOPII / 48-fpBGA / 48-µBGA
V62C1162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Functional Description
The V62C1162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
Memory expansion is provided by an active LOW (CE)
and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
TSOPII / 48-fpBGA / 48-µBGA (See nest page)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 2048
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15 A16
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.2 May 2001 V62C1162048L(L)
1

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V62C1162048L(L)
MOSEL VITELIC V62C1162048L(L)M
1 23 4 5 6
Top View
12
34
A BLE
OE
A0
A1
B I/O9
BHE
A3
A4
C I/O10
I/O11
A5
A6
D VSS
I/O12
NC
A7
E VCC
I/O13
NC
A16
F I/O15
I/O14
A14
A15
G I/O16
NC
A12
A13
H NC A8 A9
Note: NC means no Ball.
A10
Top View
56
A2 NC
CE
I/O1
I/O2 I/O3
I/O4 VCC
I/O5 VSS
I/O6 I/O7
WE
A11
I/O8
NC
48 Ball - 6 x 8 µ BGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SIDE VIEW
aaa
D
D1
6
5
4
3
2
1
ABCDE FGH
BOTTOM VIEW
b
SOLDER BALL
REV. 1.2 May 2001 V62C1162048L(L)
2
SYMBOL
A
A1
b
c
D
D1
E
E1
e
aaa
UNIT:MM
1.10+0.10
0.22+0.05
0.35
0.36(TYP)
8.00+0.10
5.25
6.00+0.10
3.75
0.75TYP
0.10

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V62C1162048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
-55
-40
Maximum
+4.0
1.0
+150
+85
Unit
V
W
0C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16
H X X X X High-Z
High-Z
L L H L H Data Out High-Z
L L H H L High-Z Data Out
L L H L L Data Out Data Out
L X L L L Data In Data In
L X L L H Data In High-Z
L X L H L High-Z Data In
L H H X X High-Z
High-Z
L X X H H High-Z High-Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Mode
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Output Disable
Output Disable
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**)
Parameter
Supply Voltage
Input Voltage
Symbol Min
Typ
Max
Unit
VCC 1.8 2.0
Gnd 0.0 0.0
2.2
0.0
V
V
VIH 1.6 - VCC + 0.2 V
VIL -0.5* - 0.4 V
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature
REV. 1.2 May 2001 V62C1162048L(L)
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V62C1162048L(L)
DC Operating Characteristics (Vcc =1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Output Leakage
Current
Sym Test Conditions
IILII
Vcc = Max,
Vin = Gnd to Vcc
IILOI
CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc
-70 -85 -100 -120
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
- 1 - 1 - 1 - 1 µA
Operating Power
Supply Current
ICC CE = VIL , VIN = VIH or VIL , - 5 - 5 - 5 - 5 mA
IOUT = 0
Average Operating
Current
ICC1 IOUT = 0mA,
Min Cycle, 100% Duty
- 35 - 35 - 30 - 30 mA
ICC2 CE < 0.2V
IOUT = 0mA,
- 3 - 3 - 3 - 3 mA
Cycle Time=1µs, Duty=100%
Standby Power Supply ISB CE = VIH
Current (TTL Level)
- 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply ISB1 CE > Vcc - 0.2V
Current (CMOS Level)
VIN < 0.2V or
VIN > Vcc- 0.2V
- 10 - 10 - 10 - 10 µA
L - 2 - 2 - 2 - 2 µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage VOH IOH = -1 mA
1.6 - 1.6 - 1.6 - 1.6 -
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Input Capacitance
I/O Capacitance
Symbol
Cin
CI/O
Test Condition
Vin = 0V
Vin = Vout = 0V
Max
7
8
Unit
pF
pF
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 1.6V
5ns
1.0V
Output Load Condition
70ns/85ns
Load for 100ns/120ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
CL*
TTL
Figure A. * Including Scope and Jig Capacitance
REV. 1.2 May 2001 V62C1162048L(L)
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V62C1162048L(L)
Read Cycle (9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Sym -70
-85 -100 -120 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC 70 - 85 - 100 - 120 -
ns
Address Access Time
tAA - 70 - 85 - 100 - 120 ns
Chip Enable Access Time
tACE - 70 - 85 - 100 - 120 ns
Output Enable Access Time
tOE
- 40 - 40 - 50 -
60
ns
Output Hold from Address Change
tOH 10 - 10 - 10 - 10 -
ns
Chip Enable to Output in Low-Z
tLZ 10 - 10 - 10 - 10 -
ns 4,5
Chip Disable to Output in High-Z
tHZ
- 30 - 35 - 40 -
45
ns 3,4,5
Output Enable to Output in Low-Z
tOLZ 5 - 5 - 5 - 5
-
ns
Output Disable to Output in High-Z
tOHZ - 25 - 30 - 35 - 40 ns
BLE, BHE Enable to Output in Low-Z
tBLZ 5 - 5 - 5 - 5
-
ns 4,5
BLE, BHE Disable to Output in High-Z tBHZ - 25 - 30 - 35 - 40 ns 3,4,5
BLE, BHE Access Time
tBA
- 40 - 40 - 50 -
60
ns
Write Cycle (11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
Symbol -70 -85 -100 -120
Min Max Min Max Min Max Min Max
tWC 70 - 85 - 100 - 120 -
tCW
60 - 70 - 80 - 90
-
tAW
60 - 70 - 80 - 90
-
tAS
0-0-0- 0
-
tWP
50 - 60 - 70 - 80
-
tWR
0-0-0- 0
-
tDW
30 - 35 - 40 - 45
-
tDH
0-0-0- 0
-
tWHZ - 30 - 35 - 40 - 45
tOW
5-5-5- 5
-
tBW
60 - 70 - 80 - 90
-
5
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 1.2 May 2001 V62C1162048L(L)