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MOSEL VITELIC V62C18164096
256K x 16, CMOS STATIC RAM
PRELIMINARY
Features
s High-speed: 85, 100 ns
s Ultra low CMOS standby current of 2µA (max.)
s Fully static operation
s All inputs and outputs directly TTL compatible
s Three state outputs
s Ultra low data retention current (VCC = 1.0V)
s Operating voltage: 1.8V – 2.3V
s Packages
– 48-Ball CSP BGA (8mm x 10mm)
Description
The V62C18164096 is a 4,194,304-bit static
random-access memory organized as 262,144
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
Functional Block Diagram
A0 VCC
GND
A6
Row
1024 x 4096
Decoder
Memory Array
A7
A8
A9
I/O1
I/O16
Input
Data
Circuit
Column I/O
Column Decoder
UBE
LBE
OE
WE
CE1
CE2
Control
Circuit
Device Usage Chart
Operating Temperature
Range
0°C to 70°C
–40°C to +85°C
Package Outline
B
A10
Access Time (ns)
85 100
••
••
A17
Power
L LL
••
Temperature
Mark
Blank
I
V62C18164096 Rev. 1.2 June 2000
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MOSEL VITELIC
Pin Descriptions
A0–A17
Address Inputs
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE Output Enable Input
The output enable input is active LOW. With the
chip enabled, when OE is Low and WE High, data
will be presented on the I/O pins. The I/O pins will
be in the high impedance state when OE is High.
V62C18164096
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
WE Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O1–I/O16 Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
VCC
GND
Power Supply
Ground
Pin Configurations (Top View)
48 BGA
1 23456
A
B
C
D
E
F
G
H
TOP VIEW
123
A BLE OE A0
B I/O9 BHE A3
C I/O10 I/O11 A5
4 56
A1 A2 CE2
A4 CE1 I/O1
A6 I/O2 I/O3
D VSS I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
Note: NC means no connect.
TOP VIEW
V62C18164096 Rev. 1.2 June 2000
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MOSEL VITELIC
V62C18164096
Part Number Information
V 62 C 18 16 4096
MOSEL-VITELIC
MANUFACTURED
SRAM
FAMILY
62 = STANDARD
C = CMOS PROCESS
OPERATING
VOLTAGE
DENSITY
4096K PWR.
SPEED
TEMP.
PKG
BLANK = 0°C to 70°C
I = -40°C to +85°C
85 ns
100 ns
18 = 1.8V 2.3V
ORGANIZATION
16 = 16-bit
B = BGA
L = LOW POWER
LL = DOUBLE LOW POWER
Absolute Maximum Ratings (1)
Symbol Parameter
Commercial
Industrial
Units
VCC
VN
VDQ
TBIAS
TSTG
Supply Voltage
Input Voltage
Input/Output Voltage Applied
Temperature Under Bias
Storage Temperature
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
VCC + 0.3
-10 to +125
-55 to +125
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
VCC + 0.3
-65 to +135
-65 to +150
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance* TA = 25°C, f = 1.0MHz
Symbol Parameter
Conditions Max. Unit
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 0V
VI/O = 0V
6 pF
8 pF
NOTE:
1. This parameter is guaranteed and not tested.
Truth Table
Mode
Standby
CE1 CE2 OE
HXX
Standby
XLX
Output Disable L H X
Output Disable L H H
Read
LHL
Read
LHL
Read
LHL
Write
LHX
Write
LHX
Write
LHX
NOTE:
X = Dont Care, L = LOW, H = HIGH
I/O9-16
I/O1-8
WE UBE LBE Operation Operation
XX X
High Z
High Z
XX X
High Z
High Z
XH H
High Z
High Z
HX X
High Z
High Z
HL
L
HL H
HH
L
LL L
LLH
LH L
DOUT
DOUT
High Z
DIN
DIN
High Z
DOUT
High Z
DOUT
DIN
High Z
DIN
V62C18164096 Rev. 1.2 June 2000
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MOSEL VITELIC
V62C18164096
DC Electrical Characteristics (over all temperature ranges, VCC = 1.8V 2.3V)
Symbol
VIL
VIH
IIL
IOL
VOL
VOH
Parameter
Input LOW Voltage(1,2)
Input HIGH Voltage(1)
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
Test Conditions
VCC = Max, VIN = 0V to VCC
VCC = Max, CE = VIH, VOUT = 0V to VCC
VCC = Min, IOL = 2.1mA
VCC = Min, IOH = -0. 1mA
Min. Typ. Max. Units
-0.3 0.4
V
1.6 VCC + 0.3 V
-1 1 µA
-1 1 µA
— — 0.4 V
VCC 0.4 — — V
Symbol Parameter
Power Com.(3) Ind.(3) Units
ICC1 Average Operating Current, CE1 = VIL, CE2 = VCC 0.2V, Output Open, f = fmax 25
VCC = Max.
f = 1 MHz 2
30 mA
3
ISB TTL Standby Current
CE VIH, VCC = Max., f = 0
L 0.4 0.5 mA
LL 0.3 0.3
ISB1 CMOS Standby Current, CE1 VCC 0.2V, CE2 < 0.2V
VIN VCC 0.2V or VIN 0.2V, VCC = Max., f = 0
L5
LL 2
7 µA
3
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. VIL (Min.) = -3.0V for pulse width < 20ns.
3. Maximum values.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Timing Reference Levels
Output Load
0 to 1.6V
5 ns
0.9V
see below
AC Test Loads and Waveforms
TTL
CL*
* Includes scope and jig capacitance
CL = 30 pF + 1 TTL Load
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CHANGING:
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
OFFSTATE
V62C18164096 Rev. 1.2 June 2000
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MOSEL VITELIC
V62C18164096
Data Retention Characteristics
Symbol
VDR
ICCDR
Parameter
VCC for Data Retention
CE1 VCC 0.2V, CE2 < 0.2V, VIN VCC 0.2V,
or VIN 0.2V
Data Retention Current
CE1 VDR 0.2V, CE2 < 0.2V, VIN VCC 0.2V,
or VIN 0.2V, VDR = 1.0V
Coml
Ind.
tCDR
Chip Deselect to Data Retention Time
tR Operation Recovery Time (see Retention Waveform)
NOTES:
1. tRC = Read Cycle Time
2. TA = +25°C.
Power
L
LL
L
LL
Min.
1.0
0
tRC(1)
Typ.(2)
1
0.5
Max.
2.3
3
1.5
5
2
Low VCC Data Retention Waveform (CE Controlled)
Units
V
µA
ns
ns
Data Retention Mode
VCC
1.8V
VDR 1V
1.8V
tCDR
tR
CE1
1.6V
CE1 VCC 0.2V
1.6V
V62C18164096 Rev. 1.2 June 2000
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