These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE Output Enable Input
The output enable input is active LOW. With the
chip enabled, when OE is Low and WE High, data
will be presented on the I/O pins. The I/O pins will
be in the high impedance state when OE is High.
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
WE Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O1–I/O16 Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
Pin Configurations (Top View)
A BLE OE A0
B I/O9 BHE A3
C I/O10 I/O11 A5
A1 A2 CE2
A4 CE1 I/O1
A6 I/O2 I/O3
D VSS I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
Note: NC means no connect.
V62C18164096 Rev. 1.2 June 2000