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V62C3161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
Functional Description
• Ultra Low-power consumption
- Active: 40mA ICC at 55ns
- Stand-by: 5 µA (CMOS input/output)
1 µA (CMOS input/output, L version)
• 55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.7V to 3.3V Power Supply
• Tri-state output
• Automatic power-down when deselected
TheV62C3161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
• Available in 44 pin TSOP (II) Package
Logic Block Diagram
TSOP(II)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BLE
BHE
CE
Pre-Charge Circuit
Memory Array
1024 X 1024
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A15 18
A14 19
A13 20
A12 21
NC 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.1 April 2001 V62C3161024L(L)
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V62C3161024L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
PT
Tstg
Tbias
Minimum
-0.5
-55
-40
Maximum
+4.6
1.0
+150
+85
Unit
V
W
0C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
Truth Table
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16
H X X X X High-Z
High-Z
L L H L H Data Out High-Z
L L H H L High-Z Data Out
L L H L L Data Out Data Out
L X L L L Data In Data In
L X L L H Data In High-Z
L X L H L High-Z Data In
L H H X X High-Z
High-Z
L X X H H High-Z High-Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Mode
Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Output Disable
Output Disable
* Key: X = Don’t Care, L = Low, H = High
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
Parameter
Supply Voltage
Input Voltage
Symbol Min
Typ
Max
Unit
VCC 2.7 3.0
Gnd 0.0 0.0
3.3
0.0
V
V
VIH 2.2 - VCC + 0.5 V
VIL -0.5* - 0.6 V
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature
REV. 1.1 April 2001 V62C3161024L(L)
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V62C3161024L(L)
DC Operating Characteristics (Vcc = 3V+10%, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Output Leakage
Current
Sym Test Conditions
IILI
Vcc = Max,
Vin = Gnd to Vcc
IILO
CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc
-55 -70 -85 -100
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
- 1 - 1 - 1 - 1 µA
Operating Power
Supply Current
ICC CE = VIL , VIN = VIH or VIL , - 3 - 3 - 3 - 3 mA
IOUT = 0
Average Operating
Current
ICC1 IOUT = 0mA,
Min Cycle, 100% Duty
- 40 - 35 - 30 - 30 mA
ICC2 CE < 0.2V
IOUT = 0mA,
- 3 - 3 - 3 - 3 mA
Cycle Time=1µs, Duty=100%
Standby Power Supply ISB CE = VIH
Current (TTL Level)
- 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply ISB1 CE > Vcc - 0.2V
Current (CMOS Level)
VIN < 0.2V or
VIN > Vcc- 0.2V
L - 5 - 5 - 5 - 5 µA
LL - 1 - 1 - 1 - 1 µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage VOH IOH = -2 mA
2.4 - 2.4 - 2.4 - 2.4 -
V
Capacitance (f = 1MHz, TA = 25oC)
Parameter*
Symbol
Input Capacitance
Cin
I/O Capacitance
CI/O
Test Condition
Vin = 0V
Vin = Vout = 0V
Max
7
8
Unit
pF
pF
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.6V to 2.2V
5ns
1.4V
Output Load Condition
55ns/70ns/85ns
Load for 100ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
CL*
TTL
Figure A. * Including Scope and Jig Capacitance
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V62C3161024L(L)
Read Cycle (9) (Vcc = 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Sym -55 -70 -85 -100 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC 55 - 70 - 85 - 100 -
ns
Address Access Time
tAA - 55 - 70 - 85 - 100 ns
Chip Enable Access Time
tACE - 55 - 70 - 85 - 100 ns
Output Enable Access Time
tOE
- 35 - 40 - 40 -
50
ns
Output Hold from Address Change
tOH 10 - 10 - 10 - 10 -
ns
Chip Enable to Output in Low-Z
tLZ 10 - 10 - 10 - 10 -
ns 4,5
Chip Disable to Output in High-Z
tHZ
- 25 - 30 - 35 -
40
ns 3,4,5
Output Enable to Output in Low-Z
tOLZ 5 - 5 - 5 - 5
-
ns
Output Disable to Output in High-Z
tOHZ - 25 - 25 - 30 - 35 ns
BLE, BHE Enable to Output in Low-Z
tBLZ 5 - 5 - 5 - 5
-
ns 4,5
BLE, BHE Disable to Output in High-Z tBHZ - 25 - 25 - 30 - 35 ns 3,4,5
BLE, BHE Access Time
tBA
- 35 - 40 - 40 -
50
ns
Write Cycle (11) (Vcc = 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
Symbol -55 -70 -85 -100 Unit Note
Min Max Min Max Min Max Min Max
tWC
55 - 70 - 85 - 100 -
ns
tCW
50 - 60 - 70 - 80 -
ns
tAW
50 - 60 - 70 - 80 -
ns
tAS
0-0-0- 0 -
ns
tWP
45 - 50 - 60 - 70 -
ns
tWR
0-0-0- 0 -
ns
tDW
25 - 30 - 35 - 40 -
ns
tDH
0-0-0- 0 -
ns
tWHZ - 25 - 30 - 35 - 40 ns
tOW
5-5-5- 5 -
ns
tBW
50 - 60 - 70 - 80 -
ns
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V62C3161024L(L)
Timing Waveform of Read Cycle 1 (Address Controlled)
Address
Data Out
tOH
Previous Data Valid
tRC
tAA
Timing Waveform of Read Cycle 2
Address
CE
(BLE/BHE)
OE
Data Out
High-Z
tAA
tACE
tLZ(4,5)
tBA
tBLZ(4,5)
tOE
tOLZ
tRC
Data Valid
tHZ(3,4,5)
tBHZ(3,4,5)
tOHZ
Data Valid
tOH
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = VIL.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
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