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INTEGRATED CIRCUITS
DATA SHEET
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V
input/output tolerant; 3-state
Product specification
Supersedes data of 2003 Jan 30
2003 Dec 08

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Philips Semiconductors
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
Product specification
74LVC16244A;
74LVCH16244A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out
architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bushold (74LVCH16244A only).
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC(H)16244A is a high-performance, low power,
low voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 Volt. These features allow the use of
these devices as a mixed 3.3 and 5 V environment.
The 74LVC(H)16244A is a 16-bit non-inverting buffer/line
driver with 3-state outputs. The device can be used as four
4-bit buffers, two 8-bit buffers or one 16-bit buffer. The
device features four Output Enables (1OE, 2OE, 3OE and
4OE), each controlling four of the 3-state outputs. A HIGH
on nOE causes the outputs to assume a high-impedance
OFF-state.
The 74LVC(H)16244A is identical to the 74LVC16240A
but has non-inverting outputs.
The 74LVCH16244A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
CI
CPD
propagation delay nAn to nYn
3-state output enable time nOE to nYn
3-state output disable time nOE to nYn
input capacitance
power dissipation capacitance per gate
CONDITIONS
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
VCC = 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
3.0
3.5
3.7
5.0
UNIT
ns
ns
ns
pF
12 pF
4.0 pF
2003 Dec 08
2

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Philips Semiconductors
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
Product specification
74LVC16244A;
74LVCH16244A
FUNCTION TABLE
See note 1.
INPUT
nOE
L
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
nAn
L
H
X
OUTPUT
nYn
L
H
Z
ORDERING INFORMATION
TYPE NUMBER
74LVC16244ADL
74LVCH16244ADL
74LVC16244ADGG
74LVCH16244ADGG
74LVC16244AEV
74LVCH16244AEV
TEMPERATURE RANGE
40 to +125 °C
40 to +125 °C
40 to +125 °C
40 to +125 °C
40 to +125 °C
40 to +125 °C
PACKAGE
PINS PACKAGE MATERIAL CODE
48 SSOP48 plastic SOT370-1
48 SSOP48 plastic SOT370-1
48 TSSOP48 plastic SOT362-1
48 TSSOP48 plastic SOT362-1
56 VFBGA56 plastic SOT702-1
56 VFBGA56 plastic SOT702-1
2003 Dec 08
3

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Philips Semiconductors
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
Product specification
74LVC16244A;
74LVCH16244A
PINNING
SYMBOL
PIN
1OE
1
n.c.
1Y0 2
1Y1 3
GND
4, 10, 15, 21, 28, 34, 39, 45
1Y2 5
1Y3 6
VCC 7, 18, 31, 42
2Y0 8
2Y1 9
2Y2 11
2Y3 12
3Y0 13
3Y1 14
3Y2 16
3Y3 17
4Y0 19
4Y1 20
4Y2 22
4Y3 23
4OE
24
3OE
25
4A3 26
4A2 27
4A1 29
4A0 30
3A3 32
3A2 33
3A1 35
3A0 36
2A3 37
2A2 38
2A1 40
2A0 41
1A3 43
1A2 44
1A1 46
1A0 47
2OE
48
BALL
A1
A2, A3, A4, A5, K2, K3, K4, K5
B2
B1
B3, B4, D3, D4, G3, G4, J3, J4
C2
C1
C3, H3, C4, H4
D2
D1
E2
E1
F1
F2
G1
G2
H1
H2
J1
J2
K1
K6
J5
J6
H5
H6
G5
G6
F5
F6
E6
E5
D6
D5
C6
C5
B6
B5
A6
DESCRIPTION
output enable input (active LOW)
not connected
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
data output
output enable input (active LOW)
output enable input (active LOW)
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
data input
output enable input (active LOW)
2003 Dec 08
4

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Philips Semiconductors
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
Product specification
74LVC16244A;
74LVCH16244A
1OE 1
1Y0 2
1Y1 3
GND 4
1Y2 5
1Y3 6
VCC 7
2Y0 8
2Y1 9
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
VCC 18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
16244
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 VCC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
mna706
Fig.1 Pin configuration SSOP48 and TSSOP48.
16244
K
J
H
G
F
E
D
C
B
A
ball A1 1 2 3 4 5 6
index area
001aaa196
Fig.2 Pin configuration VFBGA56.
2003 Dec 08
5