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INTEGRATED CIRCUITS
74LVC16374A/74LVCH16374A
16-bit edge triggered D-type flip-flop with
5 Volt tolerant inputs/outputs (3-State)
Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook
1998 Mar 17
Philips
Semiconductors

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Philips Semiconductors
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
74LVC16374A/
74LVCH16374A
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High impedance when VCC = 0
PIN CONFIGURATION
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
1Q6 11
38 1D6
DESCRIPTION
The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. The 74LVC16374A consists of 2 sections of
eight positive edge-triggered flip-flops. A clock (CP) input and an
output enable (OE) are provided for each octal. Inputs can be driven
from either 3.3V or 5V devices. In 3-State operation, outputs can
handle 5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The flip-flops will store the state of their individual D-inputs that meet
the set-up and hold time requirements on the LOW-to-HIGH CP
transition.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
The 74LVCH16374A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
SW00074
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
Cp to Qn
CL = 50pF
VCC = 3.3V
fMAX
Maximum clock frequency
CI Input capacitance
CPD Power dissipation capacitance per flip-flop VCC = 3.3V1
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
48-Pin Plastic SSOP Type III
–40°C to +85°C
74LVC16374A DL
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74LVC16374A DGG
48-Pin Plastic SSOP Type III
–40°C to +85°C
74LVCH16374A DL
48-Pin Plastic TSSOP Type II
–40°C to +85°C
74LVCH16374A DGG
TYPICAL
3.8
150
5.0
30
UNIT
ns
MHz
pF
pF
NORTH AMERICA
VC16374A DL
VC16374A DGG
VCH16374A DL
VCH16374A DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
1998 Mar 17
2 853-2028 19111

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Philips Semiconductors
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
74LVC16374A/
74LVCH16374A
PIN DESCRIPTION
PIN NUMBER SYMBOL
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17,
19, 20, 22, 23
1Q0 to 1Q7
GND
VCC
2Q0 to 2Q7
24 2OE
25
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
48
2CP
2D0 to 2D7
1D0 to 1D7
1CP
NAME AND FUNCTION
Output enable input
(active LOW)
3-State flip-flop outputs
Ground (0V)
Positive supply voltage
3-State flip-flop outputs
Output enable input
(active LOW)
Clock input
Data inputs
Data inputs
Clock input
LOGIC SYMBOL
1 24
1OE 2OE
47 1D0
1Q0
46 1D1
44 1D2
1Q1
1Q2
43 1D3
41 1D4
1Q3
1Q4
40 1D5
38 1D6
1Q5
1Q6
37 1D7
1Q7
36 2D0
2Q0
35 2D1
2Q1
33 2D2
2Q2
32 2D3
2Q3
30 2D4
2Q4
29 2D5
2Q5
27 2D6
2Q6
26 2D7
2Q7
1CP 2CP
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
48 25
SW00075
LOGIC DIAGRAM
1D0
1CP
1OE
DQ
CP
FF1
1Q0
TO 7 OTHER CHANNELS
2D0
2CP
2OE
FUNCTION TABLE
OPERATING MODES
nOE
INPUTS
nCP
Load and read register
L°
L°
Load register and disable outputs
H
H
°
°
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high impedance OFF-state
° = LOW-to-HIGH CP transition
DQ
CP
FF9
2Q0
TO 7 OTHER CHANNELS
SW00076
INTERNAL
nDx FLIP-FLOPS
lL
hH
lL
hH
OUTPUTS
Q0 to Q7
L
H
Z
Z
1998 Mar 17
3

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Philips Semiconductors
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
74LVC16374A/
74LVCH16374A
LOGIC SYMBOL (IEEE/IEC)
1OE
1CLK
2OE
2CLK
1
48
24
25
1D0 47
1D1 46
1D2 44
43
1D3
1D4 41
1D5 40
1D6 38
1D7 37
2D0 36
2D1 35
2D2 33
2D3 32
2D4 30
29
2D5
2D6 27
2D7 26
1EN
C1
2EN
C2
1D
1
2D 2
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
11 1Q6
12 1Q7
13 2Q0
14 2Q1
16 2Q2
17 2Q3
19 2Q4
20 2Q5
22 2Q6
23 2Q7
SW00077
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VI
VO
Tamb
tr, tf
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC input voltage range; output HIGH or LOW state
DC output voltage range; output 3-State
Operating free-air temperature range
Input rise and fall times
BUS HOLD CIRCUIT
VCC
Data Input
To internal circuit
SW00044
CONDITIONS
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
LIMITS
MIN MAX
2.7 3.6
1.2 3.6
0 5.5
0 VCC
0 5.5
–40 +85
0 20
0 10
UNIT
V
V
V
°C
ns/V
1998 Mar 17
4

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Philips Semiconductors
16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
74LVC16374A/
74LVCH16374A
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
VCC DC supply voltage
IIK DC input diode current
VI t 0
VI DC input voltage
Note 2
IOK DC output diode current
VO uVCC or VO t 0
DC output voltage; output HIGH or LOW state Note 2
VO DC output voltage; output 3-State
Note 2
–0.5 to +6.5
–50
–0.5 to +6.5
"50
–0.5 to VCC +0.5
–0.5 to 6.5
V
mA
V
mA
V
IO
IGND, ICC
Tstg
PTOT
DC output source or sink current
DC VCC or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
VO = 0 to VCC
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
"50
"100
–65 to +150
500
500
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
TEST CONDITIONS
VIH
VIL
VOH
VOL
II
IOZ
Ioff
ICC
ICC
HIGH level Input voltage
LOW level Input voltage
HIGH level output voltage
LOW level output voltage
Input leakage current
3-State output OFF-state current
Power off leakage supply
Quiescent supply current
Additional quiescent supply
current per input pin
VCC = 1.2V
VCC = 2.7 to 3.6V
VCC = 1.2V
VCC = 2.7 to 3.6V
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
VCC = 3.6V; VI = 5.5V or GND6
VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND
VCC = 0.0V; VI or VO = 5.5V
VCC = 3.6V; VI = VCC or GND; IO = 0
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
LIMITS
Temp = -40°C to +85°C
MIN TYP1 MAX
VCC
2.0
GND
0.8
VCC*0.5
VCC*0.2
VCC*0.6
VCC*0.8
VCC
0.40
0.20
0.55
"0.1 "5
0.1 "5
"10
0.1 20
UNIT
V
V
V
V
µA
µA
µA
µA
5 500 µA
1998 Mar 17
5