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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784915B, 784916B
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD784915B, 784916B are members of the NEC 78K/IV Series of microcontrollers equipped with a high-
speed 16-bit CPU and are versions with improved electrical characteristics of the µPD784915A, 784916A of the
µPD784915 Subseries.
This series contains many peripheral hardware units ideal for VCR control, such as a multi-function timer unit
(super timer unit) suitable for software servo control and VCR analog circuits.
A one-time PROM version of the µPD784916B, the µPD78P4916, is also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD784915 Subseries User’s Manual - Hardware: U10444E
78K/IV Series User’s Manual - Instruction: U10905E
FEATURES
• High instruction execution speed realized by 16-bit CPU core
• Minimum instruction execution time: 250 ns (with 8-MHz internal clock)
• High internal memory capacity
Part Number
µPD784915B
µPD784916B
ROM
49152 bytes
63488 bytes
RAM
1280 bytes
• VCR analog circuits conforming to VHS Standard
• CTL amplifier
• RECCTL driver (rewritable)
• CFG amplifier
• DFG amplifier
• DPG comparator
• DPFG separation circuit (ternary separation circuit)
• Reel FG comparator (2 channels)
• CSYNC comparator
• Timer unit (super timer unit) for servo control
• Serial interface: 2 channels (3-wire serial I/O)
• A/D converter: 12 channels (conversion time: 10 µs)
• Low-frequency oscillation mode: main system clock frequency = internal clock frequency
• Low-power dissipation mode: CPU can operate with a subsystem clock.
• Supply voltage range: VDD = 2.7 to 5.5 V
• Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current
APPLICATIONS
Control system/servo/timer of VCR
Unless mentioned otherwise, the µPD784916B is described as the representative product.
The information in this document is subject to change without notice
Document No. U13118EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
11999986

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µPD784915B, 784916B
ORDERING INFORMATION
Part Number
µPD784915BGF-xxx-3BA
µPD784916BGF-xxx-3BA
Package
100-pin plastic QFP (14 x 20 mm)
100-pin plastic QFP (14 x 20 mm)
Remark xxx indicates ROM code suffix.
Product Development of 78K/IV Series
: Under mass production
: Under development
Standard
µPD784026
Enhanced A/D,
16-bit timer,
and power
management
I2C bus supported
µPD784038Y
µPD784038
Internal memory capacity was enhanced
Pin compatible with µPD784026
Multimaster I2C bus supported
µPD784216Y
µPD784216
100-pin
I/O and internal memory capacity
was enhanced
Multimaster I2C bus supported
µPD784225Y
µPD784225
80-pin,
ROM correction was enhanced
Multimaster I2C bus supported
µPD784218Y
µPD784218
Internal memory capacity was enhanced
ROM correction was added
µPD784054
ASSP
µPD784955
DC inverter control
µPD784046
On-chip 10-bit A/D
µPD784908
On-chip IEBusTM
Controller
µPD78F4943
For CD-ROM,
56 Kbytes of flash memory
Multimaster I2C bus supported
µPD784928Y
µPD784928
µPD784915
On-chip software servo control
VCR analog circuit, enhanced timer
Function of the µPD784915 was
enhanced
2

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µPD784915B, 784916B
Function List (1/2)
Item
Internal ROM capacity
Internal RAM capacity
Operating clock
Minimum instruction
execution time
I/O ports
Real-time output port
Super
timer
unit
Timer/counter
Capture register
VCR special
circuit
General-purpose
timer
PWM output
Serial interface
A/D converter
µPD784915B
µPD784916B
49152 bytes
63488 bytes
1280 bytes
16 MHz (internal clock: 8 MHz)
Low frequency oscillation mode: 8 MHz (internal clock: 8 MHz)
Low power dissipation mode: 32.768 kHz (subsystem clock)
250 ns (with 8-MHz internal system clock)
input : 8
54 I/O : 46
11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)
Timer/counter
TM0 (16 bits)
TM1 (16 bits)
FRC (22 bits)
TM3 (16 bits)
UDC (5 bits)
EC (8 bits)
EDV (8 bits)
Compare register
3
3
-
2
1
4
1
Capture register
Remark
-
1
6
1
-
- For HSW signal generation
- For CFG signal division
Input signal
CFG
DFG
HSW
VSYNC
CTL
TREEL
SREEL
Number of bits
22
22
16
22
16
22
22
Measurable cycle
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
Operating edge
↑↓
↑↓
↑↓
↑↓
↑↓
• VSYNC separation circuit, HSYNC separation circuit
• VISS detection, wide aspect detection circuits
• Field identification circuit
• Head amplifier switch/chroma rotation output circuit
Timer
TM2 (16 bits)
TM4 (16 bits)
TM5 (16 bits)
Compare register
1
1 (capture/compare)
1
Capture register
1
• 16-bit accuracy : 3 channels (carrier frequency: 62.5 kHz)
• 8-bit accuracy : 3 channels (carrier frequency: 62.5 kHz)
3-wire serial I/O: 2 channels
• BUSY/STRB control (1 channel only)
8-bit resolution × 12 channels, conversion time: 10 µs
3