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DDAATATASSHHEETET
MOS INTEGRATED CIRCUIT
µPD78C10A, 78C11A, 78C12A
8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)
DESCRIPTION
The µPD78C11A is a CMOS 8-bit microprocessor which can integrate 16-bit ALU, ROM, RAM, an A/D converter,
a multi-function timer/event counter, and a general-purpose serial interface into a single chip, then expand the
memory (ROM/RAM) up to 60K bytes externally. The µPD78C10A is a ROM-less product of the µPD78C11A, and can
directly address the external memory up to 64k bytes. The µPD78C12A is a product which has more built-in ROM
capacity than the µPD78C11A, and its memory (ROM/RAM) can be externally extended up to 56K bytes. The
µPD78C10A, µPD78C11A, and µPD78C12A operated at low power consumption, because they have a CMOS
construction. Also, they can hold data with low power consumption by using standby function.
On-chip PROM products, µPD78CP14 and µPD78CP18 which are ideal for evaluation or preproduction use during
system development, early start-up and short-run multiple-device production of application sets, are available.
FEATURES
Abundant 159 types of instructions : 87AD series instruction set, multiplication/division instructions,
16-bit operation instructions
Instruction cycle : 0.8 µs (at 15 MHz operation)
On-chip ROM : 4096W × 8 (µPD78C11A), 8192W × 8 (µPD78C12A)
Non (µPD78C10A)
On-chip RAM : 256W × 8
High-precision 8-bit A/D converter : 8 analog inputs
General-purpose serial interface : Asynchronous, synchronous, I/O interface mode
Multi-function 16-bit timer/event counter
Two 8-bit timers
I/O lines : 32 (µPD78C10A), 44 (µPD78C11A, 78C12A)
Interrupt function (external - 3, internal - 8) : Non-maskable interrupt × 1, maskable interrupt × 10
Standby function : HALT mode, hardware/software STOP mode
Zero-cross detection function : (2 inputs)
On-chip pull-up resistor (port A, B, C: µPD78C11A, 78C12A only) by mask option
Caution The µPD78C10A does not hava a mask option.
Document No. IC-2678C
(O. D. No. IC-7769E)
Date Published February 1995 P
Printed in Japan
The information in this document is subject to change without notice.
The mark 5 shows major revised points.
© 1990

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µPD78C10A,78C11A,78C12A
ORDERING INFORMATION
Ordering Code
Package
µPD78C10ACW
µPD78C10AGF-3BE
µPD78C10AGQ-36
µPD78C10AL
µPD78C11ACW-×××
µPD78C11AGF-×××-3BE
µPD78C11AGQ-×××-36
µPD78C11AGQ-×××-37
µPD78C11AL-×××
µPD78C12ACW-×××
µPD78C12AGF-×××-3BE
µPD78C12AGQ-×××-36
µPD78C12AGQ-×××-37
µPD78C12AL-×××
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin plastic QUIP
68-pin plastic QFJ ( 950 mil)
64-pin plastic shirink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin plastic QUIP
64-pin plastic QUIP straight
68-pin plastic QFJ ( 950 mil)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin plastic QUIP
64-pin plastic QUIP straight
68-pin plastic QFJ ( 950 mil)
On-Chip ROM
None
None
None
None
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
2

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µPD78C10A,78C11A,78C12A
PIN CONFIGURATION (TOP VIEW)
For µPD78C10ACW, µPD78C10AGQ-36, µPD78C11ACW-×××, µPD78C11AGQ-×××-36/37, µPD78C12ACW-×××,
µPD78C12AGQ-×××-36/37.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TXD
PC1/RXD
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
NMI
INT1
MODE1
RESET
MODE0
X2
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64 VDD
63 STOP
62 PD7
61 PD6
60 PD5
59 PD4
58 PD3
57 PD2
56 PD1
55 PD0
54 PF7
53 PF6
52 PF5
51 PF4
50 PF3
49 PF2
48 PF1
47 PF0
46 ALE
45 WR
44 RD
43 AVDD
42 VAREF
41 AN7
40 AN6
39 AN5
38 AN4
37 AN3
36 AN2
35 AN1
34 AN0
33 AVSS
For µPD78C10AGF-3BE, µPD78C11AGF-×××-3BE, µPD78C12AGF-×××-3BE
PD3
PD4
PD5
PD6
PD7
STOP
VDD
PA0
PA1
PA2
PA3
PA4
PA5
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 32
53 31
54 30
55 29
56 28
57 27
58 26
59 25
60 24
61 23
62 22
63 21
64 20
m1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
AN4
AN3
AN2
AN1
AN0
AVSS
VSS
X1
X2
MODE0
RESET
MODE1
INT1
3