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Copyright © 1999, Power Innovations Limited, UK
TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
PROGRAMMABLE OVERVOLTAGE PROTECTION FOR ERICSSON COMPONENTS
SUBSCRIBER LINE INTERFACE CIRCUITS, SLICS
q Overvoltage Protectors for listed SLICs:-
SLIC †§
PBL 3762A/2
PBL 3762A/4
PBL 3764A/4
PBL 3764A/6
PBL 3766
PBL 3766/6
PBL 3767
PBL 3767/6
PBL 3860A/1
PBL 3860A/6
PBL 386 10/2
PBL 386 11/2
PBL 386 14/2
PBL 386 15/2
PBL 386 20/2
PBL 386 21/2
PBL 386 30/2
PBL 386 40/2
PBL 386 50/2
PBL 386 61/2
PBL 386 65/2
PBL 387 10/1
TISPPBL1
!
!
!
!
"
"
"
"
!
!
"
"
!
!
!
!
!
!
!
< 55 mA‡
< 55 mA‡
!
TISPPBL2
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
§ See Applications Information for earlier SLIC types.
‡ Use TISPPBL2 when programmed line current is
above 55 mA
q Rated for International Surge Wave Shapes
WAVE SHAPE
STANDARD
2/10 µs
1.2/50 µs
0.5/700 µs
10/700 µs
10/1000 µs
GR-1089-CORE
ITU-T K22
I3124
ITU-T K20, K21
GR-1089-CORE
ITSP
A
100
100
40
40
30
q Specified Impulse Limiting Voltage
- Voltage-Time Envelope Guaranteed
- Full -40 °C to 85 °C Temperature Range
q UL Recognized, E132482
D PACKAGE
(TOP VIEW)
(Tip) K1 1
8 K1 (Tip)
(Gate) G 2 7 A (Ground)
NC 3
6 A (Ground)
(Ring) K2
4
5 K2 (Ring)
MD6XANA
NC - No internal connection
Terminal typical application names shown in
parenthesis
P PACKAGE
(TOP VIEW)
(Tip) K1 1
8 K1 (Tip)
(Gate) G 2
7 A (Ground)
NC 3
6 A (Ground)
(Ring) K2 4
5 K2 (Ring)
MD6XAV
NC - No internal connection
Terminal typical application names shown in
parenthesis
device symbol
K1 K1
A
G1,G2
A
K2 K2
Terminals K1, K2 and A correspond to the alternative
line designators of T, R and G or A, B and C. The
negative protection voltage is controlled by the
voltage, VGG, applied to the G terminal.
SD6XAEA
q Feed-Through Package Connections
- Minimises Inductive Wiring Voltages
q Surface Mount and Through-Hole Ordering
Options
DEVICE CODE PACKAGE AND CARRIER TYPE
TISPPBLxD 8-pin Small-Outline in a Tube
TISPPBLxDR 8-pin Small-Outline on Tape and Reeled
TISPPBLxP
8-pin Plastic DIP in a Tube
† Customers are advised to obtain the latest version of the relevant Ericsson Components SLIC information to verify, before placing orders, that
the information being relied on is current.
PRODUCT INFORMATION
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1

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TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
description
The TISPPBL1 and TISPPBL2 are dual forward-conducting buffered p-gate overvoltage protectors. They are
designed to protect the Ericsson Components SLICs (Subscriber Line Interface Circuits) against overvoltages
on the telephone line caused by lightning, a.c. power contact and induction. The TISPPBLx limits voltages
that exceed the SLIC supply rail levels.
The SLIC line driver section is typically powered by a negative voltage, VBat, in the region of -10 V to -85 V.
The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the
negative supply voltage. As the protection voltage will track the negative supply voltage the overvoltage stress
on the SLIC is minimised. The TISPPBLx buffered gate design reduces the loading on the SLIC supply during
overvoltages caused by power cross and induction.
Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially
clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then
the protector will crowbar into a low voltage ground referenced on-state condition. As the overvoltage
subsides the high holding current of the crowbar prevents d.c. latchup. The difference between the TISPPBL1
and TISPPBL2 is the minimum value of holding current. The 105 mA TISPPBL1 can delatch SLIC
programmed line currents up to 55 mA and the 150 mA TISPPBL2 can delatch all programmed line current
values.
These monolithic protection devices are fabricated in ion-implanted planar vertical power structures for high
reliability and in normal system operation they are virtually transparent. The TISPPBLx is available in 8-pin
plastic small-outline surface mount package and 8-pin plastic dual-in-line package.
absolute maximum ratings, -40 °C TA 85 °C (unless otherwise noted)
RATING
Repetitive peak off-state voltage, IG = 0
Repetitive peak gate-cathode voltage, VKA = 0
Non-repetitive peak on-state pulse current (see Notes 1 and 2)
10/1000 µs (Bellcore GR-1089-CORE, Issue 2, December 1997, Section 4)
0.2/310 µs (I3124, open-circuit voltage wave shape 0.5/700 µs)
5/310 µs (ITU-T K20 & K21, open-circuit voltage wave shape 10/700 µs)
1/20 µs (ITU-T K22, open-circuit voltage wave shape 1.2/50 µs)
2/10 µs (Bellcore GR-1089-CORE, Issue 2, December 1997, Section 4)
Non-repetitive peak on-state current, 50/60 Hz (see Notes 1 and 2)
100 ms
1s
5s
300 s
900 s
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Note 1)
Operating free-air temperature range
Junction temperature
Storage temperature range
SYMBOL
VDRM
VGKRM
ITSP
VALUE
-100
-90
30
40
40
100
100
UNIT
V
V
A
ITSM
IGSM
TA
TJ
Tstg
11
4.5
2.4
0.95
0.93
40
-40 to +85
-40 to +150
-65 to +150
A
A
°C
°C
°C
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 °C TJ 85 °C. The surge may be repeated after the device returns to
its initial conditions.
2. These non-repetitive rated currents are peak values for either polarity. The rated current values may be applied either to the Ring to
Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied
simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Above
85 °C, derate linearly to zero at 150 °C lead temperature.
PRODUCT INFORMATION
2

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TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
recommended operating conditions
SEE Figure 18
C1 Gate decoupling capacitor
Series resistance for GR-1089-CORE first-level and second-level surge survival
R1a
Series resistance for GR-1089-CORE first-level surge survival
R1b
Series resistance for ITU-T recommendation K20/21
MIN TYP MAX UNIT
100 220
nF
40
25
10
electrical characteristics, -40 °C TA 85 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ID
V(BO)
t(BR)
VF
VFRM
tFR
IH
IGAS
IGAT
IGAF
IGT
VGT
CAK
Off-state current
Breakover voltage
Breakdown time
Forward voltage
Peak forward recovery
voltage
Forward recovery time
Holding current
Gate reverse current
Gate reverse current,
on state
Gate reverse current,
forward conducting
state
Gate trigger current
Gate trigger voltage
Anode-cathode off-
state capacitance
VD = VDRM, VGK = 0
TJ = -40 °C
TJ = 85 °C
IT = -20 A, 0.5/700 generator, Figure 3 test circuit (See Figure 2)
IT = -20 A, 0.5/700 generator, Figure 3 test cir-
cuit (See Figure 2)
V(BR) < -50 V
IF = 5 A, tw = 500 µs
IF = 20 A, 0.5/700 generator, Figure 3 test circuit (See Figure 2)
IF = 20 A, 0.5/700 generator, Figure 3 test
circuit (See Figure 2)
IT = -1 A, di/dt = 1A/ms, VGG = -50 V,
VGG = VGKRM, VAK = 0
VF > 5 V
VF > 1 V
TISPPBL1
TISPPBL2
TJ = -40 °C
TJ = 85 °C
IT = -0.5 A, tw = 500 µs, VGG = -50 V, TA = 25 °C
IF = 1 A, tw = 500 µs, VGG = -50 V, TA = 25 °C
IT = -5 A, tp(g) 20 µs, VGG = -50 V, TA = 25 °C
IT = -5 A, tp(g) 20 µs, VGG = -50 V, TA = 25 °C
f = 1 MHz, Vd = 1 V, IG = 0, TA = 25 °C
(see Note 3)
VD = -3 V
VD = -50 V
MIN
-105
-150
TYP
MAX
-5
-50
-70
UNIT
µA
µA
V
1 µs
3V
8V
1
10000
µs
mA
-5 µA
-50 µA
-1 mA
-10 mA
5 mA
2.5 V
110 pF
60 pF
NOTE 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
thermal characteristics
PARAMETER
RθJA Junction to free air thermal resistance
TEST CONDITIONS
Ptot = 0.8 W, TA = 25 °C
5 cm2, FR4 PCB
D Package
P Package
MIN TYP MAX UNIT
160
°C/W
100
PRODUCT INFORMATION
3

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TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
PRINCIPAL TERMINAL V-I CHARACTERISTIC
IFSP (= |ITSP|)
+i
IFSM (= |ITSM|)
IF
Quadrant I
Forward
Conduction
Characteristic
VF
GATE TRANSFER
CHARACTERISTIC
+iK
IF
VGK(BO)
VGG (Circuit VB)
-v
VD
IGT
ID
+v -iG
IGAF
+iG
I(BO)
V(BO)
IS
VS
IH
VT
IT
IGAT
IT
Quadrant III
Switching
Characteristic
ITSM
ITSP
-i
PM6XAIB
IK
IG
-iK
Figure 1 PRINCIPAL TERMINAL AND GATE TRANSFER CHARACTERISTICS
PROTECTOR MAXIMUM LIMITING VOLTAGE
vs
TIME
10
MAX VFRM = 8 V
5 1 µs
10 ms
0 Time
-50 1 µs
VGG = VB = -50 V
-60
-70 MAX V(BO) = -70 V
-80 PM6XALB
Figure 2 TRANSIENT LIMITS FOR TISPPBLx LIMITING VOLTAGE
PRODUCT INFORMATION
4

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TISPPBL1D, TISPPBL1P, TISPPBL2D, TISPPBL2P
DUAL FORWARD-CONDUCTING P-GATE THYRISTORS
FOR ERICSSON COMPONENTS SLICS
AUGUST 1997 - REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
S1 15
25
±1960 V
20 µF
20 nF
ECAT WITH E502 0.5/700 SURGE NETWORK
IMPULSE
R1 CURRENT
Hi 50 IT, IF
LIMITING
VOLTAGE
Lo VK, VF
Th4 DUT
(TISPPBLx)
Th5
R1 = ONE SECTION OF A THICK-FILM HIGH
VOLTAGE PULSE RESISTOR NETWORK
220 nF
IG
VB (VGG)
-50 V
AI6XBACB
Figure 3 TEST CIRCUIT FOR MEASUREMENT OF LIMITING VOLTAGE
E502 0.5/700 WAVEFRONT CURRENT
vs
TIME
AI6XAY
20
15
10
5
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time - µs
Figure 4 CURRENT WAVEFRONT
E502 0.5/700 WAVEFRONT di/dt
vs
TIME
AI6XAZ
80
70
60
50
40
30
20
10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Time - µs
Figure 5 CURRENT WAVEFRONT di/dt
PRODUCT INFORMATION
5