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SLA7042M AND
SLA7044M
MICROSTEPPING, UNIPOLAR PWM,
HIGH-CURRENT MOTOR CONTROLLER/DRIVER
OUT A
STROBE A
REF/ENABLE A
CNTRL SPLY A
CLOCK A
SERIAL DATA A
GROUND A
OUT A
SENSE A
SENSE B
OUT B
GROUND B
STROBE B
REF/ENABLE B
CNTRL SPLY B
CLOCK B
SERIAL DATA B
OUT B
Dwg. PK-008
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB . . . . . . . . . . . . 46 V
FET Output Voltage, VDS . . . . . . . . . . . 100 V
Control Supply Voltage, VDD . . . . . . . . . 7.0 V
Peak Output Current,
IOUTM (tw 10 µs) . . . . . . . . . . . . . . . . 5.0 A
Continuous Output Current, IOUT
SLA7042M . . . . . . . . . . . . . . . . . . . . . 1.5 A
SLA7044M . . . . . . . . . . . . . . . . . . . . . 3.0 A
Input Voltage Range,
VIN . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Reference Voltage, VREF . . . . . . . . . . . . VDD
Package Power Dissipation, PD . See Graph
Junction Temperature, TJ . . . . . . . . . +150°C
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
Tstg . . . . . . . . . . . . . . . . . . -40°C to +150°C
The SLA7042M and SLA7044M are designed for high-efficiency
and high-performance microstepping operation of 2-phase, unipolar
stepper motors. Microstepping provides improved resolution without
limiting step rates, and provides much smoother low-speed motor
operation. An automated, innovative packaging technology combined
with power NMOS FETs and monolithic CMOS logic/control circuitry
advances power multi-chip modules (PMCMs™) toward the complete
integration of motion control. Each half of these stepper motor control-
ler/drivers operate independently. The 4-bit shift registers are serially
loaded with motor phase information and output current-ratio data (eight
levels). The combination of user-selectable current-sensing resistor,
linearly adjustable reference voltage, and digitally selected output
current ratio provides users with a broad, variable range of of full, half,
and microstepping motor control (IOUT [VREF/3 • RS] • Current Ratio).
Each PMCM is rated for a maximum motor supply voltage of 46 V
and utilizes advanced NMOS FETs for the high-current, high-voltage
driver outputs. The avalanche-rated (100 V) FETs provide excellent
ON resistance, improved body diodes, and very-fast switching. The
multi-chip ratings and performance afford significant benefits and
advantages for stepper drives when compared to the higher dissipation
and slower switching speeds associated with bipolar transistors. Highly
automated manufacturing techniques provide low-cost and exception-
ally reliable PMCMs suitable for controlling and directly driving a broad
range of 2-phase, unipolar stepper motors. The SLA7042M and
SLA7044M are identical except for rDS(on) and output current ratings.
Complete applications information is given on the following pages.
PWM current is regulated by appropriately choosing current-sensing
resistors, a voltage reference, and digitally programmable current ratio.
Inputs are compatible with 5 V logic and microprocessors.
BENEFITS AND FEATURES
s Cost-Effective, Multi-Chip Solution
s ‘Turn-Key’ Motion-Control Module
s Motor Operation to 3 A and 46 V
s 3rd Generation High-Voltage FETs
s 100 V, Avalanche-Rated NMOS
s Low rDS(on) NMOS Outputs
s Advanced, Improved Body Diodes
s Microstepping Unipolar Drive
s High-Efficiency, High-Speed PWM
s Independent PWM Current Control
(2-Phase)
s Digitally Programmable PWM
Current Control
s Low Component-Count PWM Drive
s Low Internal-Power Dissipation
s Electrically Isolated Power Tab
s Logic IC- and µP-Compatible
Inputs
s Machine-Insertable Package
Always order by complete part number: SLA7042M .

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SLA7042M AND SLA7044M
MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS
REF/ENABLE 3 14
+
V DD – 1
FUNCTIONAL BLOCK DIAGRAM
ENABLE
CONTROL
SUPPLY
4
15
VDD
V REF
D/A
+
OUT A/B
1
11
OUT A/B
8
18
STROBE 2 13
DATA 6 17
CLOCK 5 16
LATCHES
SHIFT REG
CHANNEL A PIN NUMBERS
CHANNEL B PIN NUMBERS
PHASE
12
7
GROUND
10
9
SENSE
Dwg. FK-006
Note that channels A and B are electrically isolated.
25
ALLOWABLE PACKAGE
POWER DISSIPATION
20
15
10
R θJM = 5.0°C/W
5 R θJA = 28°C/W
0
25
50 75 100
TEMPERATURE in °C
125 150
Dwg. GK-018-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1995, 1998 Allegro MicroSystems, Inc.

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SLA7042M AND SLA7044M
MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS
DC ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V unless otherwise noted.
Limits
Characteristic
FET Leakage Current
FET ON Voltage
Symbol
IDSS
VDS(ON)
FET ON Resistance
rDS(on)
Body Diode Forward Voltage VSD
Control Supply Voltage
Control Supply Current
Logic Input Voltage
Logic Input Current
REF/ENABLE Input Voltage
VDD
IDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
VREF/EN
REF/ENABLE Input Current
Step Reference
Current Ratio
IREF/EN
SRCR
First Bit Entered (X) = Phase
Second Bit Entered = LSB
Last Bit Entered = MSB
Test Conditions
VDS = 100 V
SLA7042M, IOUT = 1.2 A
SLA7044M, IOUT = 3 A
SLA7042M, IOUT = 1.2 A
SLA7044M, IOUT = 3 A
SLA7042M, IOUT = –1.2 A
SLA7044M, IOUT = –3 A
Operating
Each controller, VDD = 5.5 V
VIN(1) = VDD
VIN(0) = 0
DATA, CLOCK, STROBE, and OUT Enabled
DATA, CLOCK, STROBE, and OUT Disabled
0 V VREF/EN 5 V
DATA Input = 000X
DATA Input = 001X
DATA Input = 010X
DATA Input = 011X
DATA Input = 100X
DATA Input = 101X
DATA Input = 110X
DATA Input = 111X
Min Typ Max
— — 4.0
— — 800
— — 855
— — 0.67
— — 0.285
— — 1.2
— — 1.6
4.5 5.0 5.5
— — 7.0
3.5 — —
— — 1.5
— — 1.0
— — –1.0
0.4 — 2.5
VDD - 1
0
20
40
55.5
71.4
83
91
100
±1.0
NOTE: Negative current is defined as coming out of (sourcing) the specified device pin.
Units
mA
mV
mV
V
V
V
mA
V
V
µA
µA
V
V
µA
%
%
%
%
%
%
%
%
TYPICAL AC CHARACTERISTICS at TA = +25°C, VDD = 5 V, IOUT = 1 A, Logic Levels are VDD and
Ground
PWM OFF Time
Output RiseTime
Output Fall Time
Strobe-to-Output Switching Time
tr
tf
tpd
DATA Input = 001X ................................................................. 7 µs
DATA Input = 010X ................................................................. 7 µs
DATA Input = 011X ................................................................. 9 µs
DATA Input = 100X ................................................................. 9 µs
DATA Input = 101X ................................................................. 9 µs
DATA Input = 110X ................................................................ 11 µs
DATA Input = 101X ................................................................ 11 µs
10% to 90% ........................................................................... 0.5 µs
90% to 10% ........................................................................... 0.1 µs
50% to 50% ........................................................................... 0.7 µs

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SLA7042M AND SLA7044M
MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS
CLOCK
D
DATA
AB
C
D
AB
C
E
STROBE
F
Dwg. WK-002
SERIAL PORT TIMING CONDITIONS
(TA = +25°C, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Falling Edge (Data Set-Up Time) ........... 150 ns
B. Minimum Data Active Time After Clock Falling Edge (Data Hold Time) .................. 150 ns
C. Minimum Data Pulse Width ...................................................................................... 350 ns
D. Minimum Clock Pulse Width .................................................................................... 350 ns
E. Minimum Time Between Clock and Strobe Falling Edges ....................................... 650 ns
F. Minimum Strobe Pulse Width ................................................................................... 500 ns
APPLICATIONS INFORMATION
The SLA7042M and SLA7044M modules integrate two
CMOS controller ICs and four NMOS FETs. Each half of the
device operates independently, although the CLOCK inputs
may be connected together and the STROBE inputs may be
connected together. Pulling VREF/EN low (<2.5 V) allows the 4-
bit shift registers to be serially loaded with motor phase and
output currrent ratioing data.
The first bit selects the motor phase (logic high = Output A
or B, logic low = Output A or B); the next three bits determine
the motor current ratio (eight steps, 0% to 100%). The internal
D/A converter, in conjunction with a current-sensing resistor
and input reference voltage, completes the microstepping
current control.
Pulling VREF/EN high (within 1 V of VDD) resets the shift
register and latches to turn the MOS drivers OFF and inhibits
the serial DATA input.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

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SLA7042M AND SLA7044M
MICROSTEPPING,
UNIPOLAR PWM, HIGH-CURRENT
MOTOR CONTROLLER/DRIVERS
REGULATING THE PWM OUTPUT CURRENT
The output current (and motor coil current) waveform
is illustrated in Figure 1. Setting the maximum PWM
current trip point to meet the specified full-step running
current for the motor, IOUT max (DATA input = 111X =
100% ratio), requires only a current-sensing resistor, RS,
and an input reference voltage, VREF/EN, between 0.4 V
and 2.5 V.
IOUT max
VREF/EN
3 • RS
PHASE A
0
PHASE A
I OUT
Dwg. WK-001
FIGURE 1.␣ PHASE A COIL CURRENT WAVEFORM
SERIAL DATA INPUT ENABLE
In a minimum-component application, a voltage divider
provides VREF/EN and an npn transistor provides the
required pull-down to enable the serial data input as
shown in Figure 2.
IOUT max
R2
R1 + R2
Vb
3 • RS
µP STEPPER MOTOR CONTROL
Alternative REFERENCE/ENABLE input configura-
tions provide for more complete motor control. A tri-state
logic element and a voltage divider allows a fixed refer-
ence voltage, with both output disable and data enable
functions. Complete µP control is usually accomplished
with a D/A converter as shown in Figure 3. Here, digital
control provides an output disable (>VDD - 1 V), VREF, and
VEN (<2.5 V).
ENABLE
DATA
SERIAL DATA
VDD
V BB
B
Vb
TO CHANNEL B
R1
VREF/EN
D/A
R2
PWM
OFF-TIME
CONTROL
Ø
CONTROL
LOGIC
AA
DRIVE
SENSE
B
RS
FIGURE 2.␣ PWM CONTROL (RUN MODE)
Dwg. EK-011