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P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D converters
Rev. 04 — 09 February 2004
Objective data
1. General description
The P89LPC933/934/935 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes
instructions in two to four clocks, six times the rate of standard 80C51 devices. Many
system-level functions have been incorporated into the P89LPC933/934/935 in order
to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
s 4 kB/8 kB byte-erasable Flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 256-byte RAM data memory. (P89LPC935 also includes a 512-byte auxiliary
on-chip RAM).
s 512-byte customer Data EEPROM on chip allows serialization of devices, storage
of set-up parameters, etc. (P89LPC935)
s Dual 4-input multiplexed 8-bit A/D converters (P89LPC935, single A/D on
P89LPC934/933). Two analog comparators with selectable inputs and reference
source.
s Two 16-bit counter/timers (each may be configured to toggle a port output upon
timer overflow or to become a PWM output) and a 23-bit system timer that can
also be used as a Real-Time clock.
s Enhanced UART with fractional baudrate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
s Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions (P89LPC935).
s High-accuracy internal RC oscillator option allows operation without external
oscillator components.The RC oscillator option is selectable and fine tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s 28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to
26 I/O pins while using on-chip oscillator and reset options.

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Philips Semiconductors
P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
s A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for
all instructions except multiply and divide when executing at 12 MHz. This is 6
times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
s Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
s Serial Flash In-System Programming (ISP) allows coding while the device is
mounted in the end application.
s In-Application Programming of the Flash code memory. This allows changing the
code in a running application.
s Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.
s Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be configured as an interrupt.
s Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical Power-down
current is 1 µA (total Power-down with analog functions disabled).
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
s Configurable on-chip oscillator with frequency range options selected by user
programmed Flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 12 MHz.
s Oscillator Fail Detect. The Watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
s Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
s Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.
s LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
s Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.
s Only power and ground connections are required to operate the
P89LPC933/934/935 when internal reset and RC oscillator options are selected.
s Four interrupt priority levels.
s Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s Schmitt trigger port inputs.
s Second data pointer.
s Emulation support.
9397 750 12853
Objective data
Rev. 04 — 09 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1: Ordering information
Type number
Package
Name
Description
P89LPC933FDH TSSOP28 plastic thin shrink small outline package;
28 leads; body width 4.4 mm
P89LPC934FDH TSSOP28 plastic thin shrink small outline package;
28 leads; body width 4.4 mm
P89LPC935FA PLCC28 plastic leaded chip carrier; 28 leads
P89LPC935FDH TSSOP28 plastic thin shrink small outline package;
28 leads; body width 4.4 mm
P89LPC935FHN
HVQFN28 plastic thermal enhanced very thin quad flat
package; no leads; 28 terminals;
body 6 × 6 × 0.85 mm
Version
SOT361-1
SOT361-1
SOT261-2
SOT361-1
SOT788-1
3.1 Ordering options
Table 2: Part options
Type number
Flash memory
P89LPC933FDH
4 kB
P89LPC934FDH
8 kB
P89LPC935FA
8 kB
P89LPC935FDH
8 kB
P89LPC935FHN
8 kB
Temperature range
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
Frequency
0 to 12 MHz
0 to 12 MHz
0 to 12 MHz
0 to 12 MHz
0 to 12 MHz
9397 750 12853
Objective data
Rev. 04 — 09 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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4. Block diagram
P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC933/934/935
ACCELERATED 2-CLOCK 80C51 CPU
CRYSTAL
OR
RESONATOR
Fig 1. Block diagram.
4 kB/8 kB
CODE FLASH
256-BYTE
DATA RAM
INTERNAL
BUS
512-BYTE
AUXILIARY RAM
(P89LPC935)
512-BYTE
DATA EEPROM
(P89LPC935)
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CONFIGURABLE
OSCILLATOR
CPU
CLOCK
ON-CHIP
RC
OSCILLATOR
UART
I2C
ADC0(P89LPC935)
/DAC0
ADC1/DAC1
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
ANALOG
COMPARATORS
CCU (CAPTURE/
COMPARE UNIT)
(P89LPC935)
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aaa563
9397 750 12853
Objective data
Rev. 04 — 09 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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5. Pinning information
5.1 Pinning
P89LPC933/934/935
8-bit microcontroller with accelerated two-clock 80C51 core
DAC0/P2.0 1
P2.1 2
KBI0/CMP2/P0.0 3
P1.7 4
P1.6 5
RST/P1.5 6
VSS 7
XTAL1/P3.1 8
CLKOUT/XTAL2/P3.0 9
INT1/P1.4 10
SDA/INT0/P1.3 11
SCL/T0/P1.2 12
MOSI/P2.2 13
MISO/P2.3 14
28 P2.7
27 P2.6
26 P0.1/CIN2B/KBI1/AD10
25 P0.2/CIN2A/KBI2/AD11
24 P0.3/CIN1B/KBI3/AD12
23 P0.4/CIN1A/KBI4/AD13/DAC1
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
002aaa565
Fig 2. P89LPC933/934 TSSOP28 pin configuration.
9397 750 12853
Objective data
handbook, halfpage
AD03/DAC0/ICB/P2.0 1
AD02/OCD/P2.1 2
AD01/KBI0/CMP2/P0.0 3
AD00/OCC/P1.7 4
OCB/P1.6 5
RST/P1.5 6
VSS 7
XTAL1/P3.1 8
CLKOUT/XTAL2/P3.0 9
INT1/P1.4 10
SDA/INT0/P1.3 11
SCL/T0/P1.2 12
MOSI/P2.2 13
MISO/P2.3 14
28 P2.7/ICA
27 P2.6/OCA
26 P0.1/CIN2B/KBI1/AD10
25 P0.2/CIN2A/KBI2/AD11
24 P0.3/CIN1B/KBI3/AD12
23 P0.4/CIN1A/KBI4/AD13/DAC1
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
002aaa759
Fig 3. P89LPC935 TSSOP28 pin configuration.
Rev. 04 — 09 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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