8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
s A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for
all instructions except multiply and divide when executing at 12 MHz. This is 6
times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
s Serial Flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
s Serial Flash In-System Programming (ISP) allows coding while the device is
mounted in the end application.
s In-Application Programming of the Flash code memory. This allows changing the
code in a running application.
s Watchdog timer with separate on-chip oscillator, requiring no external
components. The watchdog prescaler is selectable from 8 values.
s Low voltage reset (Brownout detect) allows a graceful system shutdown when
power fails. May optionally be conﬁgured as an interrupt.
s Idle and two different Power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical Power-down
current is 1 µA (total Power-down with analog functions disabled).
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.
s Conﬁgurable on-chip oscillator with frequency range options selected by user
programmed Flash conﬁguration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 12 MHz.
s Oscillator Fail Detect. The Watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
s Programmable port output conﬁguration options: quasi-bidirectional, open drain,
s Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value
of the pins match or do not match a programmable pattern.
s LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the
s Controlled slew rate port outputs to reduce EMI. Outputs have approximately
10 ns minimum ramp times.
s Only power and ground connections are required to operate the
P89LPC933/934/935 when internal reset and RC oscillator options are selected.
s Four interrupt priority levels.
s Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s Schmitt trigger port inputs.
s Second data pointer.
s Emulation support.
9397 750 12853
Rev. 04 — 09 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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