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S-7600A TCP/IP NETWORK PROTOCOL STACK LSI Revision 1.2
Hardware Specification
S-7600A
TCP/IP Network Protocol LSI
Seiko Instruments USA Inc.
Phone +1-909-934-9334
Fax +1-909-975-5699
2990 West Lomita Boulevard
Torrance, California 90505
Seiko Instruments Inc.

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S-7600A
Hardware Specification
TABLE OF CONTENTS
1. INTRODUCTION .............................................................................................................................................. 1
1.1. PRODUCT OVERVIEW .................................................................................................................................. 1
1.2. FEATURES.................................................................................................................................................... 1
1.3. BENEFITS ............................................................................................................................... ...................... 1
1.4. TRADEMARKS............................................................................................................................................... 2
1.5. DEFINITIONS ............................................................................................................................... ................. 2
1.6. APPLICABLE DOCUMENTS ........................................................................................................................... 2
1.7. CAUTIONS .................................................................................................................................................... 2
2. FUNCTIONAL BLOCK DIAGRAM................................................................................................................ 3
3. TERMINALS ..................................................................................................................................................... 4
3.1. PIN ASSIGNMENT ......................................................................................................................................... 4
3.2. PACKAGE DIMENSIONS................................................................................................................................ 5
3.3. PIN DESCRIPTION ........................................................................................................................................ 6
3.4. PIN CONFIGURATION ................................................................................................................................... 7
4. ELECTRICAL CHARACTERISTICS............................................................................................................. 8
4.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 8
4.2. RECOMMENDED OPERATING CONDITIONS ................................................................................................. 8
4.3. DC CHARACTERISTICS................................................................................................................................ 9
4.4. POWER CURRENT CONSUMPTION .............................................................................................................. 9
5. MPU INTERFACE .......................................................................................................................................... 10
5.1. OVERVIEW ................................................................................................................................................. 10
5.2. PARALLEL INTERFACE ............................................................................................................................... 10
5.2.1. 68k Family MPU Mode .................................................................................................................... 11
5.2.1.1. Write Cycle Timing ..................................................................................................................................... 11
5.2.1.2. Read Cycle Timing ............................................................................................................................... ...... 12
5.2.2. x80 Family MPU Mode .................................................................................................................... 13
5.2.2.1. Write Cycle Timing ..................................................................................................................................... 13
5.2.2.2. Read Cycle Timing ............................................................................................................................... ...... 14
5.3. SERIAL INTERFACE .................................................................................................................................... 15
5.3.1. Write Cycle Timing........................................................................................................................... 15
5.3.2. Read Cycle Timing........................................................................................................................... 16
5.4. INTERRUPT................................................................................................................................................. 17
6. MEMORY REQUIREMENTS ....................................................................................................................... 18
6.1. OVERVIEW ................................................................................................................................................. 18
6.2. MEMORY INTERFACE ARCHITECTURE....................................................................................................... 18
6.3. MEMORY MAP............................................................................................................................................ 19
7. S-7600A REGISTER DEFINITIONS ........................................................................................................... 20
7.1. OVERVIEW ................................................................................................................................................. 20
7.2. IAPI REGISTER MAP ................................................................................................................................. 20
7.3. REGISTER DEFINITIONS............................................................................................................................. 23
7.3.1. Revision Register (0x00)................................................................................................................ 23
7.3.2. General Control Register (0x01)................................................................................................... 23
7.3.3. Generic Socket Location Register (0x02).................................................................................... 24
7.3.4. Master Interrupt (0x04)................................................................................................................... 24
7.3.5. Serial Port Configuration / Status Register (0x08) ..................................................................... 25
7.3.6. Serial Port Interrupt Register (0x09) ............................................................................................ 27
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S-7600A
Hardware Specification
7.3.7. Serial Port Interrupt Mask Register (0x0A) ................................................................................. 27
7.3.8. Serial Port Data Register (0x0B) .................................................................................................. 28
7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................................ 28
7.3.10. Our IP Address Registers (0x10-0x13)...................................................................................... 28
7.3.11. Clock Divider Registers (0x1C-0x1D) ........................................................................................ 29
7.3.12. Index Register (0x20)................................................................................................................... 29
7.3.13. Type of Service Register (TOS) (0x21) ..................................................................................... 29
7.3.14. Socket Config Status Low Register (0x22) ............................................................................... 30
7.3.15. Socket Status Mid Register (0x23)............................................................................................. 32
7.3.16. Socket Activate Register (0x24) ................................................................................................. 33
7.3.17. Socket Interrupt Register (0x26)................................................................................................. 33
7.3.18. Socket Data Available Register (0x28) ...................................................................................... 34
7.3.19. Socket Interrupt Mask Low Register (0x2A) ............................................................................. 35
7.3.20. Socket Interrupt Mask High Register (0x2B) ............................................................................ 35
7.3.21. Socket Interrupt Low Register (0x2C)........................................................................................ 36
7.3.22. Socket Interrupt High Register (0x2D)....................................................................................... 36
7.3.23. Socket Data Register (0x2E) ...................................................................................................... 37
7.3.24. TCP Data Send and Buffer Out Length Registers (0x30 - 0x31)........................................... 37
7.3.25. Buffer In Length Registers (0x32-0x33) .................................................................................... 37
7.3.26. Urgent Pointer / UDP Datagram Size Registers (0x34-0x35) ................................................ 37
7.3.27. Their Port Registers (0x36-0x37) ............................................................................................... 38
7.3.28. Our Port Registers (0x38-0x39).................................................................................................. 38
7.3.29. Socket Status High Register (0x3A) .......................................................................................... 38
7.3.30. Their IP Address Registers (0x3C-0x3F) .................................................................................. 39
7.3.31. PPP Control and Status Register (0x60)................................................................................... 40
7.3.32. PPP Interrupt Code (0x61) .......................................................................................................... 41
7.3.33. PPP Max Retry, (0x62) ................................................................................................................. 41
7.3.34. PAP String (0x64) ......................................................................................................................... 42
8. SERIAL PORT INTERFACE ........................................................................................................................ 43
8.1. OVERVIEW ................................................................................................................................................. 43
8.2. SERIAL PORT REGISTER MAP................................................................................................................... 43
8.2.1. Hardware Flow Control (RTS/CTS Handshaking)....................................................................... 44
8.2.2. Serial Port Control............................................................................................................................ 44
9. RESET FUNCTIONS ..................................................................................................................................... 45
9.1. OVERVIEW ................................................................................................................................................. 45
9.1.1. Hardware reset function.................................................................................................................. 45
9.1.2. Software reset function ................................................................................................................... 45
10. APPLICATION EXAMPLES ....................................................................................................................... 46
10.1.1. In case of x80 Family MPU with LCD Controller ....................................................................... 46
10.1.2. In case of 68k Family MPU with LCD Controller ....................................................................... 47
10.1.3. In case of Serial interface with LCD Controller .......................................................................... 48
Seiko Instruments Inc.
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S-7600A
Hardware Specification
LIST OF FIGURES
FIGURE 2.-1 BLOCK DIAGRAM ..................................................................................................................... 3
FIGURE 3.-1 PIN ASSIGNMENT .................................................................................................................... 4
FIGURE 3.-2 PACKAGE DIMENSIONS ........................................................................................................... 5
FIGURE 3.-3 CONFIGURATION OF EACH PIN ................................................................................................. 7
FIGURE 5.-4 68 FAMILY MPU WRITE TIMING ............................................................................................ 11
FIGURE 5.-5 68 FAMILY MPU READ TIMING.............................................................................................. 12
FIGURE 5.-6 X80 FAMILY MPU WRITE CYCLE TIMING .............................................................................. 13
FIGURE 5.-7 X80 FAMILY MPU READ CYCLE TIMING ................................................................................ 14
FIGURE 5.-8 SERIAL INTERFACE WRITE TIMING......................................................................................... 15
FIGURE 5.-9 SERIAL INTERFACE READ TIMING ......................................................................................... 16
FIGURE 5.-1 INT1 INTERRUPT TIMING ....................................................................................................... 17
FIGURE 6.-1 MEMORY INTERFACE ARCHITECTURE.................................................................................... 18
FIGURE 8.-1 SERIAL DATA FORMAT ......................................................................................................... 43
FIGURE 9.-1 HARDWARE RESET TIMING..................................................................................................... 45
FIGURE 9.-2 SOFTWARE RESET TIMING .................................................................................................... 45
FIGURE 10.-1 EXAMPLE FOR X80 FAMILY MPU ......................................................................................... 46
FIGURE 10.-2 EXAMPLE FOR 68K FAMILY MPU ......................................................................................... 47
FIGURE 10.-3 EXAMPLE FOR SERIAL INTERFACE........................................................................................ 48
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S-7600A
Hardware Specification
LIST OF TABLES
TABLE 3.-1 PIN ASSIGNMENT ................................................................................................................................. 4
TABLE 3.-2 PIN DESCRIPTION ................................................................................................................................ 6
TABLE 4.-1 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 8
TABLE 4.-2 RECOMMENDED OPERATING CONDITIONS ................................................................................. 8
TABLE 4.-3 DC CHARACTERISTICS ............................................................................................................. 9
TABLE 4.-4 POWER CURRENT CONSUMPTION ............................................................................................. 9
TABLE 5.-1 INTERFACE SELECTION ........................................................................................................... 10
TABLE 5.-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS ........................................................... 10
TABLE 5.-3 68K FAMILY MPU WRITE CYCLE TIMING ................................................................................. 11
TABLE 5.-4 68K FAMILY MPU READ CYCLE TIMING.................................................................................. 12
TABLE 5.-5 X80 FAMILY MPU WRITE CYCLE TIMING ................................................................................ 13
TABLE 5.-6 X80 FAMILY MPU READ CYCLE TIMING.................................................................................. 14
TABLE 5.-7 SERIAL INTERFACE WRITE CYCLE TIMING .............................................................................. 15
TABLE 5.-8 SERIAL INTERFACE READ CYCLE TIMING ................................................................................ 16
TABLE 5.-9 INTERRUPT SELECTION TABLE ................................................................................................ 17
TABLE 6.-1 S-7600A MEMORY MAP (BANK 0).......................................................................................... 19
TABLE 6.-2 S-7600A MEMORY MAP (BANK 1).......................................................................................... 19
TABLE 7.-1 IAPI REGISTER MAP.............................................................................................................. 21
TABLE 7.-2 IAPI REGISTER MAP (CONTINUED)......................................................................................... 22
TABLE 7.-3 REVISION REGISTER BIT DEFINITIONS .................................................................................... 23
TABLE 7.-4 REVISION REGISTER DESCRIPTION ........................................................................................ 23
TABLE 7.-5 GENERAL CONTROL REGISTER BIT DEFINITIONS..................................................................... 23
TABLE 7.-6 GENERAL CONTROL REGISTER DESCRIPTION ......................................................................... 23
TABLE 7.-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... 24
TABLE 7.-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION............................................................ 24
TABLE 7.-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS .................................................................... 24
TABLE 7.-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED)................................................ 25
TABLE 7.-11 CONF STATUS REGISTER BIT DEFINITIONS ........................................................................... 25
TABLE 7.-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... 26
TABLE 7.-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS............................................................ 27
TABLE 7.-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION ................................................................ 27
TABLE 7.-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS .................................................. 27
TABLE 7.-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ...................................................... 27
TABLE 7.-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10)............................................................ 28
TABLE 7.-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11)............................................................ 28
TABLE 7.-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12)............................................................ 29
TABLE 7.-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13)............................................................ 29
TABLE 7.-21 INDEX REGISTER BIT DEFINITION .......................................................................................... 29
TABLE 7.-22 INDEX REGISTER DESCRIPTION ............................................................................................. 29
TABLE 7.-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS.................................................... 30
TABLE 7.-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION ........................................................ 31
TABLE 7.-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS.................................................................. 32
TABLE 7.-26 SOCKET STATUS MID REGISTER DESCRIPTION ...................................................................... 32
TABLE 7.-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS...................................................................... 33
TABLE 7.-28 SOCKET ACTIVATE REGISTER DESCRIPTION .......................................................................... 33
TABLE 7.-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................... 33
TABLE 7.-30 SOCKET INTERRUPT REGISTER DESCRIPTION........................................................................ 34
TABLE 7.-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS .................................................................. 34
TABLE 7.-32 SOCKET DATA AVAIL REGISTER DESCRIPTION....................................................................... 34
TABLE 7.-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS.................................................. 35
TABLE 7.-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION ...................................................... 35
TABLE 7.-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS ................................................. 35
TABLE 7.-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION...................................................... 35
TABLE 7.-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................... 36
TABLE 7.-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION ................................................................ 36
TABLE 7.-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS........................................................... 36
Seiko Instruments Inc.
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