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S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3
Hardware Specification
S-7600A
TCP/IP Network Stack LSI
Components Marketing Dept.
Marketing Section 2
Phone +81-43-211-1028
Fax +81-43-211-8035
8, Nakase 1-chome, Mihama-ku
Chiba-shi, Chiba 261-8507, Japan
Seiko Instruments Inc.

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TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
TABLE OF CONTENTS
1. INTRODUCTION........................................................................................................................... 1-1
1.1. PRODUCT OVERVIEW ............................................................................................................... 1-1
1.2. FEATURES ............................................................................................................................... 1-1
1.3. BENEFITS................................................................................................................................. 1-1
1.4. TRADEMARKS........................................................................................................................... 1-2
1.5. DEFINITIONS ............................................................................................................................ 1-2
1.6. APPLICABLE DOCUMENTS ......................................................................................................... 1-2
1.7. CAUTIONS................................................................................................................................ 1-2
2. FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1
3. TERMINALS.................................................................................................................................. 3-1
3.1. PIN ASSIGNMENT...................................................................................................................... 3-1
3.2. PACKAGE DIMENSIONS ............................................................................................................. 3-2
3.3. PIN DESCRIPTION..................................................................................................................... 3-3
3.4. PIN CONFIGURATION ................................................................................................................ 3-4
4. ELECTRICAL CHARACTERISTICS............................................................................................. 4-1
4.1. ABSOLUTE MAXIMUM RATINGS.................................................................................................. 4-1
4.2. RECOMMENDED OPERATING CONDITIONS ................................................................................. 4-1
4.3. DC CHARACTERISTICS ............................................................................................................. 4-2
4.4. POWER CURRENT CONSUMPTION ............................................................................................. 4-2
5. MPU INTERFACE ......................................................................................................................... 5-1
5.1. OVERVIEW ............................................................................................................................... 5-1
5.2. PARALLEL INTERFACE............................................................................................................... 5-1
5.2.1. 68k Family MPU Mode.................................................................................................... 5-2
5.2.1.1. Write Cycle Timing ................................................................................................................5-2
5.2.1.2. Read Cycle Timing ................................................................................................................5-3
5.2.2. x80 Family MPU Mode.................................................................................................... 5-4
5.2.2.1. Write Cycle Timing ................................................................................................................5-4
5.2.2.2. Read Cycle Timing ................................................................................................................5-5
5.3. SERIAL INTERFACE ................................................................................................................... 5-6
5.3.1. Write Cycle Timing.......................................................................................................... 5-6
5.3.2. Read Cycle Timing.......................................................................................................... 5-7
5.4. INTERRUPT............................................................................................................................... 5-8
6. MEMORY REQUIREMENTS ........................................................................................................ 6-1
6.1. OVERVIEW ............................................................................................................................... 6-1
6.2. MEMORY INTERFACE ARCHITECTURE ........................................................................................ 6-1
6.3. MEMORY MAP .......................................................................................................................... 6-2
7. S-7600A REGISTER DEFINITIONS ............................................................................................. 7-1
7.1. OVERVIEW ............................................................................................................................... 7-1
7.2. IAPI REGISTER MAP................................................................................................................. 7-1
7.3. REGISTER DEFINITIONS ............................................................................................................ 7-4
7.3.1. Revision Register (0x00)................................................................................................ 7-4
7.3.2. General Control Register (0x01) .................................................................................... 7-4
7.3.3. Generic Socket Location Register (0x02) ...................................................................... 7-5
7.3.4. Master Interrupt (0x04) .................................................................................................. 7-5
7.3.5. Serial Port Configuration / Status Register (0x08) ......................................................... 7-6
7.3.6. Serial Port Interrupt Register (0x09) .............................................................................. 7-8
7.3.7. Serial Port Interrupt Mask Register (0x0A) .................................................................... 7-8
7.3.8. Serial Port Data Register (0x0B).................................................................................... 7-9
7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9
Seiko Instruments Inc.
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TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
7.3.10.
7.3.11.
7.3.12.
7.3.13.
7.3.14.
7.3.15.
7.3.16.
7.3.17.
7.3.18.
7.3.19.
7.3.20.
7.3.21.
7.3.22.
7.3.23.
7.3.24.
7.3.25.
7.3.26.
7.3.27.
7.3.28.
7.3.29.
7.3.30.
7.3.31.
7.3.32.
7.3.33.
7.3.34.
Our IP Address Registers (0x10-0x13) ...................................................................... 7-9
Clock Divider Registers (0x1C-0x1D) ...................................................................... 7-10
Index Register (0x20) ............................................................................................... 7-10
Type of Service Register (TOS) (0x21) .................................................................... 7-10
Socket Config Status Low Register (0x22)............................................................... 7-11
Socket Status Mid Register (0x23)........................................................................... 7-13
Socket Activate Register (0x24) ............................................................................... 7-14
Socket Interrupt Register (0x26) .............................................................................. 7-14
Socket Data Available Register (0x28)..................................................................... 7-15
Socket Interrupt Mask Low Register (0x2A)............................................................. 7-16
Socket Interrupt Mask High Register (0x2B)............................................................ 7-16
Socket Interrupt Low Register (0x2C) ...................................................................... 7-17
Socket Interrupt High Register (0x2D) ..................................................................... 7-17
Socket Data Register (0x2E).................................................................................... 7-18
TCP Data Send and Buffer Out Length Registers (0x30-0x31) ............................... 7-18
Buffer In Length Registers (0x32-0x33) ................................................................... 7-18
Urgent Data Pointer Registers (0x34-0x35) ............................................................. 7-18
Their Port Registers (0x36-0x37) ............................................................................. 7-19
Our Port Registers (0x38-0x39) ............................................................................... 7-19
Socket Status High Register (0x3A)......................................................................... 7-19
Their IP Address Registers (0x3C-0x3F) ................................................................. 7-20
PPP Control and Status Register (0x60).................................................................. 7-21
PPP Interrupt Code (0x61) ....................................................................................... 7-22
PPP Max Retry, (0x62).............................................................................................. 7-22
PAP String (0x64)..................................................................................................... 7-23
8. DATA COMMUNICATIONS.......................................................................................................... 8-1
8.1. OVERVIEW ............................................................................................................................... 8-1
8.2. SERIAL PORT REGISTER MAP ................................................................................................... 8-1
8.2.1. Hardware Flow Control (RTS/CTS Handshaking) .......................................................... 8-2
8.2.2. Serial Port Control........................................................................................................... 8-2
8.3. TCP/UDP DATA COMMUNICATIONS.......................................................................................... 8-3
8.3.1. TCP Data Communications ............................................................................................ 8-3
8.3.2. UDP Data Communications ............................................................................................ 8-4
9. RESET FUNCTIONS .................................................................................................................... 9-1
9.1. OVERVIEW ............................................................................................................................... 9-1
9.1.1. Hardware Reset Function ............................................................................................... 9-1
9.1.2. Software Reset Function................................................................................................. 9-1
10. APPLICATION EXAMPLES........................................................................................................ 10-1
10.1.1. In Case of x80 Family MPU with LCD Controller .......................................................... 10-1
10.1.2. In Case of 68k Family MPU with LCD Controller .......................................................... 10-2
10.1.3. In Case of Serial Interface with LCD Controller ............................................................ 10-3
ii Seiko Instruments Inc.

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TCP/IP Network Stack LSI
S-7600A
Hardware Specification Revision 1.3
LIST OF FIGURES
FIGURE 2-1 BLOCK DIAGRAM ............................................................................................................... 2-1
FIGURE 3-1 PIN ASSIGNMENT .............................................................................................................. 3-1
FIGURE 3-2 PACKAGE DIMENSIONS ...................................................................................................... 3-2
FIGURE 3-3 CONFIGURATION OF EACH PIN ........................................................................................... 3-4
FIGURE 5-1 68K FAMILY MPU WRITE TIMING ....................................................................................... 5-2
FIGURE 5-2 68K FAMILY MPU READ TIMING......................................................................................... 5-3
FIGURE 5-3 X80 FAMILY MPU WRITE CYCLE TIMING............................................................................ 5-4
FIGURE 5-4 X80 FAMILY MPU READ CYCLE TIMING.............................................................................. 5-5
FIGURE 5-5 SERIAL INTERFACE WRITE TIMING ..................................................................................... 5-6
FIGURE 5-6 SERIAL INTERFACE READ TIMING ....................................................................................... 5-7
FIGURE 5-7 INT1 INTERRUPT TIMING ................................................................................................... 5-8
FIGURE 6-1 MEMORY INTERFACE ARCHITECTURE ................................................................................. 6-1
FIGURE 8-1 SERIAL DATA FORMAT....................................................................................................... 8-1
FIGURE 9-1 HARDWARE RESET TIMING ................................................................................................ 9-1
FIGURE 9-2 SOFTWARE RESET TIMING................................................................................................. 9-1
FIGURE 10-1 EXAMPLE FOR X80 FAMILY MPU...................................................................................... 10-1
FIGURE 10-2 EXAMPLE FOR 68K FAMILY MPU...................................................................................... 10-2
FIGURE 10-3 EXAMPLE FOR SERIAL INTERFACE .................................................................................... 10-3
Seiko Instruments Inc.
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