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Rev.1.1
CR TIMER
S-8081B
The S-8081B is a CMOS CR timer developed for appliances and
industrial equipment use. It consists of a CR oscillator, a 20-stage
divider, a power-on clear circuit, a trigger input chattering rejection
circuit, an internal voltage regulator, a level shift circuit, and an output
driver. It can be used as a high-precision, long-time monostable timer.
n Features
Wide power supply operating range : 4.5 to 16.5 V
Low current consumption : 200 µA max.(C = 200 k,
R = 0.0047 µF, open output )
Time can be set by external CR
Excellent oscillation stability because of built-in voltage regulator
Power-on clear circuit is integrated
Both trigger I/O inverting operation and set/reset operation can be
performed
n Applications
Time switch
Long time delay generator
n Pin Assignment
8-pin DIP/SOP
Top view
VSS 1
SET 2
OUT 3
RESET 4
S8081B
8 VDD
7 CR
6 DISCHARGE
5 TRIGGER
n Block Diagram
Figure 1
CR 7
DIS- 6
CHARGE
TRIGGER 5
SET 2
RESET 4
Oscil-
lation
circuit
20 - stage FF
FF20
tOUT
select
Control logic
Output
level shift
3 OUT
Input chattering
rejection circuit
Input
circuit
Input
circuit
Power ON
clear circuit
8 VDD
Voltage
regulator
1 VSS
Figure 2
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CR TIMER
S-8081 B
n Timer Setting
The timer time tOUT is decided by an external resistor RT and an external capacitor CT.
tOUT=(K×RT×CT×219) sec.
K=time constant coefficient
10 stOUT10 hours (recommended)
RT50 k, CT100 pF (recommended)
Note : If other CT or RT is used than above recommended, the internal C and R influence tOUT and it becomes different
in each unit.
1 VSS
2 SET
3 OUT
VDD 8
CR 7
DISCH 6
CT**
RT*
4 RESET TRIG 5
CT : Connect between VDD and CR
RT : Connect between CR and DISCHARGE
* RT 50 k
** CT100PF
Figure 3 Connection of external CT and RT
TRIG-
GER
OUT
tOUT
tOUT
RESET
Figure 4 TRIGGER operation timing chart
SET
OUT
RESET
tOUT
tOUT
Figure 5 SET operation timing chart
tOUT=tOSC×219
tOSCK×RT×CT
(Recommended : RT50 k, CT100 pF)
n Operation
1. SET terminal
At the rise of SET terminal, OUT goes high (VDD) and frequency dividing operation starts.
This terminal has a pull-down resistor built in.
2. RESET terminal
By bringing RESET terminal high (VDD), OUT goes low (VSS) and the internal counter is reset.
Set or trigger input is ignored when reset is high.
This terminal has a pull-down resistor built in.
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CR TIMER
S-8081 B
3. TRIGGER terminal
At the rise of TRIGGER terminal, OUT level is inverted. When OUT changes from low (VSS) to high (VDD),
frequency dividing operation starts. When OUT changes from high (VDD) to low (VSS), the internal counter is
reset. When starting TRIGGER operation during setting operation, reset the S-8081B before TRIGGER input. This
terminal has a chattering rejection circuit and a pull-down resistor built in.
Chattering rejection time tosc×7
4. CR and DISCHARGE terminals
CR oscillation circuit can be constructed by connecting a timing capacitor CT between VDD and CR terminals, and
by connecting a timing resistor RT between CR and DISCHARGE terminals.
Set the oscillation period (tosc) following the formula below.
tOSC K×RT×CT
K : time constant coefficient
5. OUT terminal
At the rise of SET or TRIGGER terminal, OUT goes high (VDD) and frequency dividing operation starts. OUT goes
low (VSS) after tosc ×219.
When OUT is high (VDD) if TRIGGER rises or RESET goes high (VDD), OUT goes low (VSS) and the internal counter
is reset.
n Absolute Maximum Ratings
Table 1
Unless otherwise specified: Ta=25°C
Parameter
Power supply voltage
Input/output voltage*
Operating temperature
Storage temperature
Power dissipation
Symbol
VDD
VIN, VOUT
Topr
Tstg
PD
Conditions
VSS = 0 V
at 25°C
Ratings
Unit
18 V
VSS0.3 to VDD+0.3
30 to+85
40 to+125
V
°C
°C
300 mW
* Excluding DISCHARGE terminal
n Electrical Characteristics
Table 2
Parameter
Symbol
Conditions
Operating power supply voltage
Operating current consumption
SET, RESET, TRIGGER input
pull-down resistance
High level input voltage
Low level input voltage
High level output current
Low level output current
Low level output voltage
Time constant coefficent
Power supply voltage
CR fluctuation*
osc Temperature fluctuation*
VDD
IDD
Rdown
VIH
VIL
IOH
IOL
VOL
K
f/fosc
/ VDD
f/fosc
/ T
R=200 kOpen output
C=0.0047 µF
VIH=VDD
VOH=5.7 V VDD=8.0 V
VOL=2.3 V VDD=8.0 V
VDD=5.0 V IOUT=3.2 mA
C=0.0047 µF
R=200 k
VDD=4.5 to 16 V
C=0.0047 µF
R=200 k
Ta=20 to +60°C
C=0.0047 µF
R=200 k
VDD = 12 V, VSS = 0 V, Ta = 25°C
Min. Typ. Max. Unit
4.5 16.5 V
  200 µA
50
0.8×VDD
VSS
10
20
1.276
15
30
1.450
400
VDD
0.2×VDD
0.4
1.624
k
V
mA
V
0.05 %/V
0.10 %/°C
* Fluctuation of IC only
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CR TIMER
S-8081 B
n AC Electrical Characteristics
1. Input signal timing
Table 3
Parameter
Symbol
SET pulse width
RESET pulse width
TRIG pulse width
RESET-SET pulse interval
RESET-TRIG pulse interval
TRIG pulse interval
SET input timing
Pulse interval between timer
operation finish and SET
tS
tR
tT
tRS
tRT
tTT
tTS
tOS
Pulse interval between timer
operation finish and TRIG
tOT
tOSC : oscillating frequency, (tOSC=K×RT×CT)
VDD=12 V, VSS=0 V, Ta=25 °C
Min. Typ. Max. Unit
10   µs
10   µs
16×tOSC   µs
10   µs
10   µs
10   µs
tT+10   µs
10   µs
10   µs
SET
RESET
TRIG
OUT
tS tR tRS
tT tTS
tRT tTT
RESET input has the precedence over SET or TRIG input.
Figure 6
tOS
2. TRIG input pulse width and operation status
Table 4
VDD=12 V, VSS=0 V, Ta=25 °C
TRIG input pulse width
TRIG input pulse width16×tOSC
7×tOSC<TRIG input pulse width<16×tOSC
TRIG input pulse width7×tOSC
*TRIG operation does not always start.
tOSC : oscillating frequency
Operation
TRIG operation
Indefinite*
No TRIG operation
n Notes
1. Notes on operation
Do not start TRIGGER operation during setting operation (see Figure 7). When starting TRIGGER operation during
setting operation, reset the S-8081B before TRIGGER input.
Do not set the RESET terminal high while SET or TRIGGER terminal is at high level. Or, the S-8081B will enter
acceleration test mode. (see Figure 8)
SET
TRIGGER
OUT
SET or
TRIGGER
RESET
OUT
Figure 7
Figure 8
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CR TIMER
S-8081 B
2. Status just after power-ON
A power-on clear circuit is built in the S-8081B and it initializes this IC at power-ON. During initialization, the S-8081B
does not perform normal operation. Initialization time can not be defined clearly because it differs according to the
voltage fluctuation at power-ON. See Table 5 for reference. Pay sufficient attention to the operation just after power-
ON.
Table 5
Rise time
Initialization time*
<1 ms
1 ms
1 ms
Time duration from power-ON to the time
when VDD reaches 4.5 V.
* Time duration from power-ON. At this time, the S-8081B does not
operate normally.
3. CR oscillation
CR oscillation circuit is always operating while power supply voltage is applied.
4. VIH level of input signal
When pulling up the SET, RESET or TRIGGER terminal, pay attention to VIH level because they have pull-down
resistors built in.
n Acceleration Test Mode
The S-8081B has the acceleration test mode to check its F. F. function in a short time. This mode is performed
as follows.
(1) Put SET terminal from low to high level.
(2) After (1), put RESET terminal from low to high level.
(3) With keeping (1) and (2) status, input 511 clocks whose levels are the same as VDD from CR terminal.
(From 1st to 9th and from 11th to 19th stages of 20-stage F.F. are all high. The 20-stage F.F. starts operation at
the falling of input signal.)
(4) Put RESET terminal low.
(5) Put SET terminal low.
(6) Input 514th clock from CR terminal.
(7) 20th stage of the 20-stage F.F. goes high from low, and the OUT terminal goes low.
SET
RESET
CR
CLOCK
input
OUT
12
510 511
512 513 514
1024 1025
Figure 9
When releasing from acceleration test mode, initialize the S-8081B according to (a) or (b) below.
(a) Turn the power off, and on again.
(b) Put RESET terminal high level.
Seiko Instruments Inc.
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