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June 1995
PC16550D Universal Asynchronous
Receiver Transmitter with FIFOs
General Description
The PC16550D is an improved version of the original 16450
Universal Asynchronous Receiver Transmitter (UART)
Functionally identical to the 16450 on powerup (CHARAC-
TER mode) the PC16550D can be put into an alternate
mode (FIFO mode) to relieve the CPU of excessive software
overhead
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes All the logic is on
chip to minimize system overhead and maximize system ef-
ficiency Two pin functions have been changed to allow sig-
nalling of DMA transfers
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM
and parallel-to-serial conversion on data characters re-
ceived from the CPU The CPU can read the complete
status of the UART at any time during the functional opera-
tion Status information reported includes the type and con-
dition of the transfer operations being performed by the
UART as well as any error conditions (parity overrun fram-
ing or break interrupt)
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (216b1) and producing a 16 c clock for
driving the internal transmitter logic Provisions are also in-
cluded to use this 16 c clock to drive the receiver logic The
UART has complete MODEM-control capability and a proc-
essor-interrupt system Interrupts can be programmed to
the user’s requirements minimizing the computing required
to handle the communications link
The UART is fabricated using National Semiconductor’s ad-
vanced M2CMOS process
Can also be reset to 16450 Mode under software control
Note This part is patented
Features
Y Capable of running all existing 16450 software
Y Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29) The former CSOUT and
NC pins are TXRDY and RXRDY respectively
Y After reset all registers are identical to the 16450 reg-
ister set
Y In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO’s to reduce the number of
interrrupts presented to the CPU
Y Adds or deletes standard asynchronous communication
bits (start stop and parity) to or from the serial data
Y Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data
Y Independently controlled transmit receive line status
and data set interrupts
Y Programmable baud generator divides any input clock
by 1 to (216 b 1) and generates the 16 c clock
Y Independent receiver clock input
Y MODEM control functions (CTS RTS DSR DTR RI
and DCD)
Y Fully programmable serial-interface characteristics
5- 6- 7- or 8-bit characters
Even odd or no-parity bit generation and detection
1- 1 - or 2-stop bit generation
Baud generation (DC to 1 5M baud)
Y False start bit detection
Y Complete status reporting capabilities
Y TRI-STATE TTL drive for the data and control buses
Y Line break generation and detection
Y Internal diagnostic capabilities
Loopback controls for communications link
isolation
Break parity overrun framing error simulation
fault
Y Full prioritized interrupt system controls
Basic Configuration
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL C 8652
TL C 8652 – 1
RRD-B30M75 Printed in U S A

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1 0 ABSOLUTE MAXIMUM RATINGS
2 0 DC ELECTRICAL CHARACTERISTICS
3 0 AC ELECTRICAL CHARACTERISTICS
4 0 TIMING WAVEFORMS
5 0 BLOCK DIAGRAM
6 0 PIN DESCRIPTIONS
7 0 CONNECTION DIAGRAMS
8 0 REGISTERS
8 1 Line Control Register
8 2 Typical Clock Circuits
Table of Contents
8 0 REGISTERS (Continued)
8 3 Programmable Baud Generator
8 4 Line Status Register
8 5 FIFO Control Register
8 6 Interrupt Identification Register
8 7 Interrupt Enable Register
8 8 Modem Control Register
8 9 Modem Status Register
8 10 Scratchpad Register
8 11 FIFO Interrupt Mode Operation
8 12 FIFO Polled Mode Operation
9 0 TYPICAL APPLICATIONS
2

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1 0 Absolute Maximum Ratings
Temperature Under Bias
0 C to a70 C
Storage Temperature
b65 C to a150 C
All Input or Output Voltages
with Respect to VSS
Power Dissipation
b0 5V to a7 0V
1W
Note Maximum ratings indicate limits beyond which perma-
nent damage may occur Continuous operation at these lim-
its is not intended and should be limited to those conditions
specified under DC electrical characteristics
2 0 DC Electrical Characteristics
TA e 0 C to a70 C VDD e a5V g10% VSS e 0V unless otherwise specified
Symbol
Parameter
Conditions
VILX
VIHX
VIL
VIH
VOL
VOH
ICC(AV)
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Average Power Supply
Current
IOL e 1 6 mA on all (Note 1)
IOH e b1 0 mA (Note 1)
VDD e 5 5V TA e 25 C
No Loads on output
SIN DSR DCD
CTS RI e 2 0V
All other inputs e 0 8V
IIL Input Leakage
ICL Clock Leakage
VDD e 5 5V VSS e 0V
All other pins floating
VIN e 0V 5 5V
IOZ TRI-STATE Leakage
VILMR
MR Schmitt VIL
VIHMR
MR Schmitt VIH
Note 1 Does not apply to XOUT
VDD e 5 5V VSS e 0V
VOUT e 0V 5 25V
1) Chip deselected
2) WRITE mode
chip selected
Min
b0 5
20
b0 5
20
24
20
Max
08
VDD
08
VDD
04
15
g10
g10
Units
V
V
V
V
V
V
mA
mA
mA
g20
08
mA
V
V
Capacitance TA e 25 C VDD e VSS e 0V
Symbol
Parameter
Conditions
Min Typ Max Units
CXIN
CXOUT
CIN
COUT
CI O
Clock Input Capacitance
Clock Output Capacitance
Input Capacitance
Output Capacitance
Input Output Capacitance
fc e 1 MHz
Unmeasured pins
returned to VSS
79
79
57
68
10 12
pF
pF
pF
pF
pF
3

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3 0 AC Electrical Characteristics TA e 0 C to a70 C VDD e a5V g10%
Symbol
Parameter
Conditions
Min
tADS
Address Strobe Width
tAH Address Hold Time
tAR RD RD Delay from Address
tAS Address Setup Time
tAW WR WR Delay from Address
tCH Chip Select Hold Time
tCS Chip Select Setup Time
tCSR
RD RD Delay from Chip Select
tCSW
WR WR Delay from Select
tDH Data Hold Time
tDS Data Setup Time
tHZ RD RD to Floating Data Delay
tMR Master Reset Pulse Width
tRA Address Hold Time from RD RD
tRC Read Cycle Delay
tRCS
Chip Select Hold Time from RD RD
tRD RD RD Strobe Width
tRDD
RD RD to Driver Enable Disable
tRVD
Delay from RD RD to Data
tWA Address Hold Time from WR WR
tWC Write Cycle Delay
tWCS
Chip Select Hold Time from WR WR
tWR WR WR Strobe Width
tXH Duration of Clock High Pulse
tXL Duration of Clock Low Pulse
RC Read Cycle e tAR a tRD a tRC
WC Write Cycle e tAW a tWR a tWC
Baud Generator
(Note 1)
(Note 1)
(Note 1)
(Note 1)
100 pF loading (Note 3)
(Note 1)
(Note 1)
100 pF loading (Note 3)
100 pF loading
(Note 1)
(Note 1)
External Clock (8 Max )
External Clock (8 Max )
60
0
30
60
30
0
60
30
30
30
30
0
5000
20
125
20
125
20
150
20
100
55
55
280
280
N Baud Divisor
1
tBHD
tBLD
tHW
tLW
Receiver
Baud Output Positive Edge Delay
Baud Output Negative Edge Delay
Baud Output Up Time
Baud Output Down Time
100 pF Load
100 pF Load
fX e 8 d2 100 pF Load
fX e 8 d2 100 pF Load
75
100
tRAI Delay from Active Edge
of RD to Reset Interrupt
tRINT
Delay from RD RD
(RD RBR or RD LSR)
to Reset Interrupt
100 pF Load
tRXI Delay from RD RBR
to RXRDY Inactive
tSCD
tSINT
Delay from RCLK to Sample Time
Delay from Stop to Set Interrupt
(Note 2)
Max
100
60
60
216b1
175
175
1000
290
2000
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK
Cycles
Note 1 Applicable only when ADS is tied low
Note 2 In the FIFO mode (FCR0e1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error indication
will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 3 Charge and discharge time is determined by VOL VOH and the external loading
Note 4 These specifications are preliminary
4

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3 0 AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions Min Max
Units
Transmitter
tHR Delay from WR WR (WR THR)
to Reset Interrupt
100 pF Load
175 ns
tIR
Delay from RD RD (RD IIR) to Reset
100 pF Load
Interrupt (THRE)
250 ns
tIRS Delay from Initial INTR Reset to Transmit
Start
8
24
BAUDOUT
Cycles
tSI Delay from Initial Write to Interrupt
(Note 1)
16
24
BAUDOUT
Cycles
tSTI Delay from Stop to Interrupt (THRE)
(Note 1)
8
8
BAUDOUT
Cycles
tSXA
Delay from Start to TXRDY active
100 pF Load
8
BAUDOUT
Cycles
tWXI Delay from Write to TXRDY inactive
Modem Control
100 pF Load
195 ns
tMDO
Delay from WR WR (WR MCR) to
Output
100 pF Load
200 ns
tRIM Delay from RD RD to Reset Interrupt 100 pF Load
(RD MSR)
250 ns
tSIM
Delay from MODEM Input to Set Interrupt
100 pF Load
250 ns
Note 1 This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode
Operation)
Note 2 These specifications are preliminary
4 0 Timing Waveforms (All timings are referenced to valid 0 and valid 1)
External Clock Input (24 0 MHz Max )
AC Test Points
TL C 8652 – 2
Note 1 The 2 4V and 0 4V levels are the voltages that the inputs are driven to during AC testing
Note 2 The 2 0V and 0 8V levels are the voltages at which the timing tests are made
BAUDOUT Timing
TL C 8652 – 3
TL C 8652 – 4
5