UM6551 pdf, UM6551 데이터시트, UM6551 데이타시트

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(DUMO

UM6551 / UM6551A

.!,.i.:i;::;t'1~?:t;if~I;);fQ'0~0i~:~::;':':Ji:il~'i:!f!:,:t!:P?:1'i:;i7(ij~~jr~iil{t!~ti!!~tf01;iz;11:;;ji::~;JrJ~Y%;;~i:1~~j,I!~ Asynchronous Communication

Interface Adapter

Features

• On-chip baud rate generator: 15 programmable baud

rates derived from a standard 1.8432 MHz external

crystal (50 to 19,200 baud)

• Programmable interrupt and status register to simplify

software design

• Single +5 volt power supply

• Serial echo mode

• False start b it detect io n

• 8-bit bi-directional data bus for direct communica-

tion with the microprocessor

• External 16x clock input for non-standard baud rates

(up to 125k baud)

• Programmable: word lengths; number of stop bits;

and parity bit generation and detection

• Data set and modem control signals provided

• Parity: (odd, even, none, mark, space)

• Full-duplex or half-duplex operation

• 5,6,7,8, and 9 bit transmission

General Description

The UM6551 is an Asynchronous Communication Adapter

(ACIA) intended to provide for interfacing the 6500/6800

microprocessor families to serial communication data

sets and modems. A unique feature is the inclusion of an

on-chip programmable baud rate generator, with a crystal

being the only external component required.

Pin Configuration

Block Diagram

GND

CSo

CS)

RES

RxC

XTALl

XTAL2

RTS

CTS

TxD

DTR

RxD

RSo

RS)

R/W

1>2

TAO

DB7

DB6

DBs

DB4

DB3

DB2

DB)

DBo

DSR

DCD

VCC

¢2

R/W

CSI

RSo

RES

DBo

DB7

CTS

TxD

'iFi'Q

DCD

DSR

RxC

XTALl

XTAL2

RxD

DTR

RTS

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Absolute Maximum Ratings*

Supply Voltage vee .............. -0.3V to" +7.0V

Input/Output Voltage V IN . . . . . . . . . . -0.3V to +7 .OV

Operating Temperature Top . . . . . . . . . . . . OOC to 70°C

Storage Temperature TSTG . . . . . . . . . . -55°C to 150°C

Note:

All inputs contain protection circuitry to prevent damage

to high static charges. Care should be exercised to prevent

unnecessary application of voltages in excess of the ai'

lowable limits.

UM6551 / UM6551A

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied and exposure to absolute maximum rating

cond itions for extended periods may affect device

reliability.

D.C. Characteristics

(Vee = 5.0V ± 5%, T~ = 0-700 C, unless otherwise noted)

Characteristics

Input High Voltage

Input Low Voltage

Input Leakage Current: VIN == 0 to 5V

(¢2, RiW, RES, CSo, CS!, RSo, RS!, CTS, R x 0, oco, OSR)

Input Leakage Current for High Irnpedance State (Three State)

Output High Voltage: I lOAD == -1 OOJJ.A

(OBo-OB 7 , TxO, RxC, RTS, OTR)

Output Low Voltage: I LOAD == 1.6 rnA

(OBo-OB7 , TxO, RxC, RTS, OTR, IRQ)

Output High Current (Sourcing): VO H = 2.4 V

(OBo-OB 7 , TxO, RxC, RTS, OTR)

Output Low Current (Sinking): VOL == O.4V

(OBo-OB 7 , TxO, RxC, RTS, OTR, TAO)

Output Leakage Current (Off State): VOUT == 5V (IRQ)

Clock Capacitance ( ¢ 2)

Input Capacitance (Except XT ALl and XTAL2)

Output Capacitance

Power Dissipation (See Graph) (TA == OoC) VCC = 5.25V

200

Symbol

V IH

Vil

liN

ITSI

V OH

Min.

2.0

-0.3

2.4

Typ.

± 1.0

±2.0

Max.

Vec

0.8

±2.5

± 10.0

Units

JJ.A

Val

- 0.4 V

IOH -100 -

- JJ.A

IOl 1.6 -

- mA

IOFF

CClK

CIN

COUT

1.0 10.0

- 20

- 10

170 300

JJ.A

rnW

TYPICAL

POWER

DISSIPATION

(mW)

175

--150 ~

I"--

125

100

20 40 60 80

Figure 1. Power Dissipation vs. Temperature

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UM6551 / UM6551A

tCYC

Jr-----VIH

VIL

,,",,~""""l'\. 1r----+-----------+--""'II<l"'!'T"~~'"""'"""~~:"'I""'I"'~'I"" VIH

...... . . . .CSo. CSI. RSO. RSI

~ ~__r-----+_---------+--:--""""l ""-IoIroIoolo.-w.w.;.....IooIolo.....oIool.Iooloolo.lo..... VI L

~--------- VIH

RiW

DATA BUS ~\\~\~~~\\\~\lr\-\--\tD\c\w_\\~_,..j..=..=_--.H_~ ~VI:HL

Figure 2. Write Timing Characteristics

Write Cycle

(VCC = 5.0V ± 5%. T A = 0 to 70°C. unless otherwise noted)

Characteristics

Cycle Time

cp 2 Pu Iso Width

Address Set-Up Time

Address Hold Time

RiW Set-Up Time

RNV Hold Time

Data Bus Set- Up Time

Data Bus Hold Time

(tr and tf = 10 to 30 ns)

Symbol

tCYC

tACW

tCAH

twcw

tCWH

tDCW

tHW

UM6551

Min.

Max.

1.0 -

400 -

120 -

150 -

20 -

UM6551 A

Min.

Max.

0.5 -

200 -

70 -

60 -

20 -

Units

#J.s

Crystal Specification

1. Temperature stability ± 0.01% (00 to 70°C)

2. Characteristics at 25°C ± 2°C

a. Frequency (MHz)

1.8432

b. Frequency tolerance (± %)

0.02

c. Resonance mode

Series

d. Equivalent resistance (ohm) 400 max.

e. Drive level mW

f. Shunt capacitance pF

7 max.

g. Oscillation mode

Fundamental

No other external components should be in the

crystal circuit

Clock Generation

XTAL1 6

EXTERNAL

CLOCK

XTAL1 6

UM6551

XTAL2

INTERNAL CLOCK

EXTERAL CLOCK

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UM6551 / UM6551A

~---------------tCYC-----------------.~11

~2 ____________- J

-tCAR

""'--VIH

R/W I,-----~---------~--------------- VIH

tCDR -

DATA BUS ---------+-----l\'

tCDA

Figure 3. Read Timing Characteristics

Read Cycle

a(V cc = 5.0V ± 5%, T A = to 70°C, unless otherwise noted)

Characteristics

Cycle Time

Pulse Width (~2)

Address Set- Up Time

Address Hold Time

RNV Set-Up Time

Read Access Time (Valid Data)

Read Data Hold Time

Bus Active Time (Invalid Data)

Symbol

tCYC

tACR

tCAR

tWCR

tCDR

tHR

tCDA

UM6551

Min.

1.0

Max.

400 -

120 -

- 200

20 .-

40 -

UM6551 A

Min.

Max.

0.5 -

200 -

70 -

- 150

20 -

40 -

Units

f.1.s

Test Load·

PIN--------~-----.--~~--._--------

OPEN COLLECTOR

OUTPUT TEST LOAD

-{3kn

. I'00PF

C = 130pF MAX. FOR DBO-OB7

C =30pF MAX. FOR ALL OTHER OUTPUTS

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UM6551 / UM6551A

XTAL 1

(TRANSMIT

CLOCK INPUT)

tOLY

TxO

Note: TxO rate is 1/16 TxC rate

Figure 4a. Transmit Timing with External Clock

IRQ

(CLEAR)

Figure 4b. Interrupt and Output Timing

1 . . - - - - tcCY --~~

RxC

(INPUT)

Note: RxO rate is 1/16 RxC rate

Figure 4c. Receive External Clock Timing

Transm it/Receive Characteristics

Characteristics

Transmit/Receive Clock Rate

Transmit/Receive Clock High Time

Transmit/Receive Clock low Time

XTAl1 to Tx D Propagation Delay

Propagation Delay (RTS, DTR)

IRO Propagation Delay (Clear)

Symbol

tCCY

tCH

tCl

tDD

tDlY

tiRO

. UM6551

Min.

Max.

400*

175 -

- 500

(tr . tt = 10 to 30 ns input clocks only)

* The baud rate with external clocking is: Baud Rate = - - - -

16 x T ccy

UM6551 A

Min.

Max.

400*

175 -

- 500

Unit

Interface Signal Description

RES (Reset)

During system initialization a low on the RES input will

cause internal registers to be cleared.

.(p 2 (Input Clock)

The input clock is the system ¢ 2 clock and is used to

trigger all data transfers between the system microprocessor

and the UM6551.

R/W (ReadlWrite)

The RNV is generated by the microprocessor and is used

to control the direction of data transfers. A high on

the RNV pin allows the processor to read the data sup-

plied by the UM6551. A low on the R/W pin allows a

write to the UM655-1-.

IRQ (Interrupt Request)

The I RO pin is an interrupt signal from the interrupt

control logic. It is an open drain output, permitting

several devices to be connected to the common IRO

microprocessor input. Normally a high level, TAO goes

low when an interrupt occurs.

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