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WM8148
12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
Production Data, April 1999, Rev 4.0
DESCRIPTION
The WM8148 is a 12-bit, 12MSPS analogue front end/
digitiser IC, which interfaces to colour or monochrome linear
array CCDs or contact image sensors (CIS). The device
includes all the signal conditioning circuitry required to
process the analogue signals from the CCD or CIS prior to
the internal ADC.
Three signal-processing channels are included in the
device. Each channel features reset level clamping,
correlated double sampling (CDS), offset correction and
programmable gain amplification (PGA). The output signal
from each channel is then multiplexed into a high
performance 12-bit analogue to digital converter (ADC).
The reset level clamp and/or CDS functions can be selected
or bypassed depending on the application.
The WM8148 can be operated in several modes. The
operational mode of the device, including the sampling
scheme and power management is programmed via the
serial/parallel control interface.
Output data is presented in either 12-bit parallel or byte-
wide (8+4-bit) format.
FEATURES
Correlated double sampling
Programmable gain amplifier
Programmable input clamp voltage
Offset correction
12-bit, 12MSPS ADC
Internal voltage reference
12-bit or 8+4 bit data output mode
Single 5V supply or 5V analogue/3.3V digital supply
Programmable sample timing
Control interface compatible with previous Wolfson
AFEs
48-pin TQFP package
APPLICATIONS
Flatbed scanners
Document scanners
Multi-function peripherals (MFPs)
Colour copiers
Character recognition systems
Linear array CCDs
Contact image sensors (CIS)
BLOCK DIAGRAM
RLC MCLK VSMP
(2) (5) (7)
AVDD 1- 4
(41,28,27,3)
DVDD1-2
(1,13)
VRX VRB VRT
(32) (29) (31)
CL RS VS
TIMING CONTROL
VREF/BIAS
WM8148
RINP (36)
GINP (37)
BINP (39)
VRLC (33)
CDS
RLC
CDS
RLC
CDS
RLC
RLC 4
DAC
8 OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+
8
OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+ MUX
12-BIT
ADC
12/8
BIT
MUX
8
OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
(35,40,30,25,6)
AGND1 - 5
(8,24,4,26)
DGND1 - 4
(43) OEB
OP[11:0]
(9-12,14-21)
(48) PNS
(34) OVRD
(45) SDI/DNA
(46) SCK/RNW
(47) SEN/STB
(42) NRESET
(44) SDO
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
©1999 Wolfson Microelectronics Ltd.

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WM8148
PIN CONFIGURATION
DVDD1
RLC
AVDD4
DGND3
MCLK
AGND5
VSMP
DGND1
OP0
OP1
OP2
OP3
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
RINP
AGND1
OVRD
VRLC
VRX
VRT
AGND3
VRB
AVDD2
AVDD3
DGND4
AGND4
Production Data
ORDERING INFORMATION
DEVICE
XWM8148CFT/V
TEMP. RANGE
0 to 70oC
PACKAGE
48-pin 1mm
thick body TQFP
PIN DESCRIPTION
PIN NAME
1 DVDD1
2 RLC
TYPE
Supply
Digital input
3 AVDD4
4 DGND3
5 MCLK
Supply
Ground
Digital input
6 AGND5
7 VSMP
Ground
Digital IO
8 DGND1
9 OP0
10 OP1
11 OP2
12 OP3
13 DVDD2
14 OP4
15 OP5
16 OP6
17 OP7
18 OP8
19 OP9
20 OP10
21 OP11
Ground
Digital output
Digital output
Digital output
Digital output
Supply
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
DESCRIPTION
Digital supply (3.3V to 5V) for digital inputs and SDO.
Selects whether reset level clamp is applied, active high. If RLC is required on every
pixel then this pin can be tied high.
Analogue supply (5V).
Digital ground (0V).
Master clock. This clock is applied at N times the input pixel rate (N = 12, 8, 6, or
4 dependent on input sampling mode). MCLK is divided internally by N to generate
internal clocks and to provide the clock source for digital logic.
Analogue ground (0V).
Video sample synchronisation pulse. This pin may be either an input (default) or output.
Input: This signal is pulsed externally
to synchronise the WM8148’s video
input sample instant and the N-phase
internal clock to CCD clocks and
interface bus timing.
Output: This signal is pulsed internally to
flag the video input sample instant, to allow
the CCD clocks and interface bus to be
synchronised to the WM8148.
Digital ground (0V) for output drivers.
12-bit signal data output bus. Data is output MSB on OP[11] and LSB on pin OP[0].
See description of pins 14-21 for mode definitions.
Digital supply (3.3V-5V) for Digital IO pins and OP0 to OP3
12-bit bi-directional data bus. On pins OP[4] to OP[11], signal data is output if OEB = 0
and register write data is input if OEB = 1.
There are five main modes:
Hi-Z: when OEB = 1
Output 12-bit: twelve bit signal data output from bus
Output 8-bit muxed: signal data output on OP[11:4] at 2 ADC conversion rate
Input 8-bit: register write data input on OP[11:4]
Output 8-bit: register readback data output on OP[11:4]
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
2

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WM8148
Production Data
PIN NAME
22 NC
TYPE
DESCRIPTION
No internal connection.
23 NC
No internal connection.
24 DGND2
Ground
Digital ground (0V) for output drivers.
25 AGND4
Ground
Analogue ground (0V).
26 DGND4
Ground
Digital ground (0V).
27 AVDD3
Supply
Analogue supply (5V).
28 AVDD2
Supply
Analogue supply (5V).
29
VRB
Analogue output Lower reference voltage. This pin must be connected to AGND and VRT via decoupling
capacitors. See Recommended External Components section for details.
30 AGND3
Ground
Analogue ground (0V).
31
VRT
Analogue output Upper reference voltage. This pin must be connected to AGND and VRB via decoupling
capacitors. See Recommended External Components section for details.
32
VRX
Analogue output Input return bias voltage. This pin must be connected to AGND via decoupling
capacitors. See Recommended External Components section for details.
33 VRLC
Analogue IO
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
See Recommended External Components section for details. VRLC can be externally
driven if programmed Hi-Z.
34 OVRD Analogue input Override pin. Typically tied low externally.
The sense of this pin defines the device function on reset. Refer to the description of
pin 42 for details.
35 AGND1
Ground
Analogue ground (0V).
36 RINP Analogue input Red channel input video.
37 GINP Analogue input Green channel input video.
38 NC
No internal connection.
39 BINP Analogue input Blue channel input video.
40 AGND2
Ground
Analogue ground (0V).
41 AVDD1
Supply
Analogue supply (5V).
42 NRESET
Digital input
Reset input, active low. This signal forces a reset of all internal registers.
Registers are set to defaults if pin OVRD is tied low.
If pin OVRD is tied high then all registers are set to defaults except EN which is set to
1 and RLCEXT which is set to 0. This will turn on all analogue circuitry including the RLC
DAC buffers driving the VRLC pin.
43 OEB
Digital input
Output enable control, all outputs disabled when OEB = 1.
This pin must be externally connected.
44 SDO
Digital output
Serial Interface: register read-back,
VSMP output, setup error flag or
over-range flag (depending on control
bits SDO [1:0]).
Parallel Interface: Hi-Z, VSMP output, set-up
error flag or over-range flag (depending on
control bits SDO [1:0]).
45 SDI/DNA
Digital input
Serial interface:
serial input data signal.
Parallel interface: High = data, Low = address.
46 SCK/RNW Digital input Serial interface: serial clock signal.
Parallel interface:
High = OP[11:4] is output bus,
Low = OP[11:4] is input bus (Hi-Z).
47 SEN/STB
Digital input
Serial interface: enable pulse,
active high.
Parallel interface: strobe, active low.
48 PNS
Digital input Low = serial interface, High = parallel interface. This pin must be externally connected.
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
3

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WM8148
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly
and will be supplied in vacuum-sealed moisture barrier bags. It has been classified as having a Moisture Sensitivity Level of 2.
CONDITION
Analogue supply voltages: AVDD1 4
Digital supply voltages: DVDD1 2
Digital grounds: DGND1 4
Analogue grounds: AGND1 5
Digital inputs and SDO
Digital outputs (not SDO)
Digital IO pins
RINP, GINP, BINP
Other pins
MIN
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
MAX
GND + 7V
GND + 7V
GND + 0.3V
GND + 0.3V
DVDD1 + 0.3V
DVDD2 + 0.3V
DVDD2 + 0.3V
AVDD + 0.3V
AVDD + 0.3V
Operating temperature range: TA
Storage temperature
0°C
-50°C
+70°C
+150°C
Lead temperature (soldering, 10 seconds)
+260°C
Lead temperature (soldering, 2 minutes)
+183°C
Notes:
GND denotes the voltage of any ground pin. AVDD denotes the voltage applied to any AVDD pin.
AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade
performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
Operating temperature range
TA 0
70 °C
Digital input and output supply voltages
DVDD1 2
2.97
5
5.25
V
Analogue supply voltages
AVDD1 4
4.75
5
5.25
V
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
4

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WM8148
Production Data
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
Overall System Performance Including 12-bit ADC, PGA, Offset and CDS Functions
NO MISSING CODES GUARANTEED
Full-scale input voltage range
Max Gain
Gain = 1.0
Min Gain
Zero-scale transition error
Gain = 1.0
Full-scale transition error
Gain = 1.0
Differential non-linearity
DNL
Gain = 1.0
Integral non-linearity
INL Gain = 1.0
ANALOGUE SPECIFICATION
Input Multiplexer
Channel to channel gain matching
Input voltage range
References
VIN
0
Upper reference voltage
VRT
3.00
Lower reference voltage
VRB
1.50
Input return bias voltage
VRX
1.50
Diff. reference voltage (VRT-VRB)
VRTB
1.30
Output resistance VRT, VRB, VRX
VRT, VRB, VRX
buffers enabled
Resistance VRT to VRB
VRT, VRB buffers
disabled
500
VRX Hi-Z leakage current
VRX buffer disabled
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
VRLC DAC resolution
4
VRLC DAC step
AVDD = 5V
290
VRLC short-circuit current
VRLC output resistance
VRLC = AVDD
VRLC = 0V
VRLC = other
Offset DAC
Resolution
8
Differential non-linearity
DNL
-0.25
Integral non-linearity
INL
-0.50
Output voltage
Code 00(hex)
Code FF(hex)
Programmable Gain Amplifier. Monotonicity Guaranteed
Resolution
6
Max gain, each channel
GMAX
Min gain, each channel
GMIN
Gain error, each channel
TYP
0.413
3.0
4.13
20
20
0.25
1.0
1
3.30
1.80
1.75
1.50
2
800
75
333
5
80
80
5
0.05
0.10
-200
200
7.4
0.74
2
MAX
UNIT
1.00
V
V
V
mV
mV
LSB
LSB
AVDD
3.60
2.10
2.00
1.70
1100
1
1
370
0.25
0.50
5
%
V
V
V
V
V
µA
µA
bits
mV/step
mA
bits
LSB
LSB
mV
mV
bits
V/V
V/V
%
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
5